Virtual Multilane Power Management Orchestrator

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Solution Overview

Problem

In AI hardware systems utilizing virtual multilane architecture, idle or under-utilized multilane systems result in power drain and energy wastage due to the lack of effective power management techniques.

Innovation Solution

The implementation of an intelligent power railing system and dynamic power management module that modulates the frequency of virtual lanes based on performance and power dissipation requirements, using an orchestrator to activate and deactivate compute blocks as needed, thereby eliminating unnecessary power usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If virtual multilane architecture is utilized to improve AI processing performance, then productivity is improved, but power consumption increases due to idle or under-utilized compute blocks

Engineering Contradiction:
ImproveAI processing performanceVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic power management by modulating the frequency of virtual lanes based on actual workload demands. The system can dynamically activate or deactivate compute blocks, adjusting operational frequency from full speed to idle or completely powered-down states, thereby matching power consumption to actual processing needs while maintaining high productivity when workloads require it

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes operational parameters (frequency, power state) of virtual lanes based on utilization metrics. When lanes are idle or under-utilized, the system reduces their frequency or deactivates them entirely, transforming the parameter state from active high-power mode to low-power or sleep mode, thus resolving the contradiction between maintaining processing capability and reducing power waste

Inventive Principle:
Principle #35Parameter changes

2Reliability

If all compute blocks are kept active to ensure readiness for AI tasks, then reliability is improved, but energy wastage increases during idle periods

Engineering Contradiction:
Improvesystem readinessVSAvoidenergy wastage
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The system performs preliminary assessment of workload requirements before activating compute blocks. The orchestrator evaluates upcoming AI tasks and activates only the necessary virtual lanes and compute blocks in advance, avoiding the energy wastage of keeping all blocks continuously active while ensuring sufficient readiness for anticipated workloads

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements feedback mechanisms that monitor utilization of compute blocks and adjust power states accordingly. When utilization drops below thresholds, the system feeds back to deactivate or throttle compute blocks, maintaining reliability by keeping essential blocks ready while eliminating energy wastage from unnecessarily active blocks

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11150720B2Systems and methods for power management of hardware utilizing virtual multilane architecture
Publication Date: 2021.10.19 KUMAR ADDEPALLI SATEESH
  • US11150720B2 patent drawing
  • US11150720B2 patent drawing
  • US11150720B2 patent drawing

AI summary

Aspects of the present disclosure are presented for a power management system of a multilane AI system architecture. The system may include an orchestrator configured to control power and other operations of a lane. An uber orchestrator manages the overall system, and may know all of the multilane systems within the AI virtual multilane system that need to be active at a given frequency and power envelope for given price, and performance constraints. The orchestrator of each lane knows the compute/logic blocks that need to be active for a given AI app model AI processing chain execution. The orchestrator may be configured to send commands to turn off power to certain components that are not utilized in performing an AI execution sequence, deactivate operation to the lane when its functions are completed, and also modulate the clock frequency of a lane to fit the computation demands while minimizing power usage.