Virtual Network Pre-Arbitration for Coherent Memory Access
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Solution Overview
Problem
Multi-core systems face coherency issues due to simultaneous access to shared memory, leading to operational inefficiencies and potential outdated data retrieval, especially when software cache maintenance operations are slow or resource-intensive.
Innovation Solution
A multi-core shared memory controller (MSMC) with a snoop filter bank, cache tag bank, and memory bank is implemented, which includes a coherent slave interface, external memory master interface, and an arbiter circuit to manage memory access requests, determine snoop requests, and allocate virtual channels, ensuring coherent data access and reducing operational inefficiencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software cache maintenance operations are used to manage coherency, then coherency can be maintained, but operational efficiency deteriorates due to slow performance and excessive operational time consumption
Solution Approach 1:
The patent replaces software-based cache maintenance operations with a hardware-based coherency manager that automatically tracks and manages cache state. The coherency manager uses hardware circuits to monitor memory access requests, update snoop filter banks, and generate invalidation signals, eliminating the performance overhead of software intervention while maintaining coherency.
Solution Approach 2:
The coherency manager operates autonomously without requiring software intervention. It self-manages the tracking of cached data, generates coherency maintenance actions, and coordinates with cache controllers automatically. The system serves itself by having the hardware infrastructure handle coherency management independently from the processing cores and software layers.
2Adaptability or versatility
If multiple processing cores simultaneously access shared memory, then system functionality is enhanced, but coherency issues arise leading to outdated data retrieval
Solution Approach 1:
The coherency manager acts as an intermediary between multiple processing cores and the shared memory system. It receives memory access requests from various cores, tracks the state of cached data through snoop filter banks, and coordinates coherency maintenance actions. This intermediary layer enables multiple cores to access shared memory simultaneously while ensuring data coherency through automated tracking and invalidation mechanisms.
3Productivity
If hardware-based coherency management is implemented, then operational efficiency is improved, but device complexity increases due to additional components
Solution Approach 1:
The coherency manager is integrated within the memory controller, merging coherency management functionality with existing memory control infrastructure. The snoop filter banks are combined with cache tag banks, and the coherency manager shares the data path and interconnect resources with other memory controller components. This integration reduces the overhead of separate hardware structures while maintaining the performance benefits of hardware-based coherency management.
Data Source
AI summary
A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.