Virtual Network Pre-Arbitration for Memory Access Deadlock Avoidance
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Solution Overview
Problem
Multi-core systems face coherency issues due to simultaneous access to shared memory, leading to operational inefficiencies and outdated data retrieval, particularly when software cache maintenance operations are slow or resource-intensive.
Innovation Solution
A multi-core shared memory controller (MSMC) with a snoop filter bank, cache tag bank, and memory bank is implemented, connected through a data path with coherent slave interfaces and an external memory master interface, allowing for efficient coherency management and data access by determining snoop requests and cache hit status to ensure up-to-date data retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software cache maintenance operations are used to manage coherency, then coherency can be maintained, but operational efficiency deteriorates and access time increases
Solution Approach 1:
The patent replaces software-based cache maintenance operations with a hardware-based coherency management system. The snoop filter bank and cache tag bank are hardware structures that automatically detect and manage cache coherency through hardware logic, eliminating the need for software intervention and significantly improving operational efficiency while maintaining coherency reliability
Solution Approach 2:
The patent introduces a snoop filter bank as an intermediary component between the cache system and memory system. This intermediary structure filters and manages coherency information, enabling efficient hardware-based coherency management without requiring software cache maintenance operations
2Reliability
If software cache maintenance operations are used to manage coherency, then coherency can be maintained, but access time increases
Solution Approach 1:
The patent replaces software-based cache maintenance operations with a hardware-based coherency management system. The snoop filter bank and cache tag bank are hardware structures that automatically detect and manage cache coherency through hardware logic, eliminating the need for software intervention and significantly improving operational efficiency while maintaining coherency reliability
Solution Approach 2:
The patent implements preliminary coherency checking through the snoop filter bank before memory access operations. By pre-filtering and validating cache tags in hardware, the system determines coherency status in advance, avoiding time-consuming software operations and reducing overall access time
Data Source
AI summary
A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.