Virtual Network Pre-Arbitration for Deadlock-Free Memory Access
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Solution Overview
Problem
Multi-core systems face coherency issues due to simultaneous access to shared memory, leading to operational inefficiencies and potential outdated data retrieval, especially when software cache maintenance operations are slow or resource-intensive.
Innovation Solution
A multi-core shared memory controller (MSMC) is implemented with a snoop filter bank, cache tag bank, and memory bank, which includes a coherent slave interface, external memory master interface, and an arbiter circuit to manage memory access requests, determine snoop requests, and allocate virtual channels, ensuring coherent data access and reducing operational inefficiencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software cache maintenance operations are used to manage coherency, then coherency can be maintained, but operational efficiency deteriorates due to slow performance and excessive operational time consumption
Solution Approach 1:
The patent replaces software-based cache maintenance operations with a hardware-based coherency management system. The snoop filter bank and cache tag bank operate in hardware to automatically detect and manage cache coherency states, eliminating the need for software intervention and thereby improving operational efficiency while maintaining coherency reliability.
Solution Approach 2:
The patent introduces a snoop filter bank as an intermediary component between the cache system and memory system. This intermediary automatically filters and manages coherency information, preventing the need for full software cache maintenance operations and reducing operational overhead while ensuring coherency is maintained.
2Adaptability or versatility
If multiple processing cores simultaneously access shared memory, then system functionality is enhanced, but coherency issues arise leading to outdated data retrieval
Solution Approach 1:
The patent implements a feedback mechanism through the snoop filter bank that continuously monitors cache access states across multiple cores. When coherency violations are detected, the system automatically generates snoop requests to invalidate or update cached data, ensuring that all cores access consistent data while maintaining multi-core access capability.
Solution Approach 2:
The patent performs preliminary coherency checks by applying tags to the cache tag bank before memory access operations. This preliminary action identifies potential coherency conflicts in advance, allowing the system to prevent outdated data retrieval before it occurs while still enabling simultaneous multi-core access.
3Productivity
If hardware-based coherency management is implemented, then operational efficiency is improved, but device complexity increases due to additional components
Solution Approach 1:
The patent merges the snoop filter bank and cache tag bank into an integrated coherency management unit that works closely with the existing memory controller. This merging approach allows hardware-based coherency management to be implemented without completely redesigning the memory subsystem, thereby improving operational efficiency while limiting the increase in device complexity.
Solution Approach 2:
The patent designs the snoop filter bank and cache tag bank to serve multiple functions: they not only manage coherency but also provide caching functionality and memory address translation. This multi-functionality reduces the need for separate dedicated components, improving operational efficiency while minimizing the increase in device complexity.
Data Source
AI summary
A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.