Virtual On-Chip Memory Paging for Real-Time Processing
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Solution Overview
Problem
Conventional System-on-a-Chip (SoC) implementations face significant delays due to the need for off-chip memory retrieval, which stalls processors when accessing data not stored in on-chip cache, hindering real-time processing.
Innovation Solution
The implementation of Virtual On-Chip Memory (VOM) allows processors to access a larger Virtual Address Space (VAS) directly from on-chip memory, using a paging technique that preloads critical information in an unpaged area and substitutes pages from a larger VAS as needed, eliminating the need for off-chip memory retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If large off-chip memory is used to meet memory demands, then memory capacity is improved, but processing speed deteriorates due to substantial retrieval delays
Solution Approach 1:
The memory system is segmented into on-chip memory and off-chip memory, with on-chip memory providing fast access for critical data and off-chip memory providing large capacity. The patent divides the address space into on-chip addressable region and off-chip addressable region, allowing processors to access frequently used data from on-chip memory while maintaining large total memory capacity through off-chip memory.
Solution Approach 2:
Data is pre-loaded from off-chip memory into on-chip memory before it is needed by real-time processes. The system proactively transfers data to the faster on-chip memory, so that when real-time processes need to access the data, it is already available on-chip, eliminating retrieval delays.
2Speed
If on-chip memory is used as cache, then memory access speed is improved for cached data, but real-time processes stall when data is not in cache
Solution Approach 1:
Different regions of the memory system are assigned different qualities: on-chip memory provides high-speed access for real-time processes, while off-chip memory provides large capacity for non-real-time processes. The patent creates an unpaged area in on-chip memory specifically dedicated to real-time processes, ensuring they always have fast access to required data without stalling.
Solution Approach 2:
The system pre-loads data into the on-chip unpaged area before real-time processes need it, based on predictions of future access patterns or criticality analysis. This ensures that when real-time processes require data, it is already positioned in the fast on-chip memory, preventing stalls and maintaining real-time reliability.
3Speed
If on-chip memory size is increased, then real-time processing is improved, but manufacturing complexity increases
Solution Approach 1:
Instead of creating one large on-chip memory, the patent segments the memory into on-chip and off-chip portions, with the on-chip portion optimized for real-time processing and the off-chip portion providing additional capacity. This segmentation allows real-time processes to benefit from fast on-chip access while avoiding the manufacturing complexity of integrating very large memories on-chip.
Data Source
AI summary
A “virtual on-chip memory” that provides advantages as compared to an on-chip memory that utilizes a cache. In accordance with the invention, when a CPU attempts to access a memory address that is not on-chip, the access is aborted and the abort is handled at a page level. A single page table is utilized in which each entry constitutes an address in the virtual address space that will be mapped to a page of on-chip memory. The CPU obtains the missing data, updates the page table, and continues execution from the aborted point. Because aborts are handled at the page level rather than the line level, the virtual on-chip memory is less expensive to implement than a cache. Furthermore, critical real-time applications can be stored within a non-virtual portion of the memory space to ensure that they are not stalled.