Virtual Partition Cell for Hierarchical IC Verification
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Solution Overview
Problem
Hierarchical integrated circuit design verification tools face challenges in managing complexity and achieving fast turnaround times for large-scale designs, as existing methods require significant computational resources and do not adequately utilize design hierarchy to improve scalability.
Innovation Solution
The introduction of virtual partition cells within the hierarchical integrated circuit design allows for the creation of additional hierarchy levels, enabling distributed processing and reducing memory footprint by dividing the workload of large parent cells into virtual partition cells, which can process overlapping child cells independently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hierarchical verification tools use existing design hierarchy to process large-scale integrated circuit designs, then the processing structure is maintained, but computational resources increase to hundreds and thousands of CPUs and memory footprint grows, failing to achieve fast turnaround time
Solution Approach 1:
The patent divides large parent cells into multiple virtual partition cells, creating a finer-grained hierarchy. Each virtual partition cell can be processed independently by different threads or processing units, enabling parallel processing without requiring hundreds or thousands of CPUs. This segmentation reduces the computational burden on each processing unit while maintaining overall processing capability.
Solution Approach 2:
The patent implements nested hierarchy by inserting virtual partition cells within existing design hierarchy levels. Virtual partition cells are nested inside parent cells, which themselves contain child cells, creating multiple levels of nesting. This allows verification tools to process designs at different hierarchy levels simultaneously, improving scalability and reducing memory footprint by only loading necessary portions of the design into memory at each level.
2Adaptability or versatility
If virtual partition cells are inserted to create additional hierarchy levels, then scalability and memory footprint are improved, but the cell hierarchy structure becomes more complex with overlapping child cells
Solution Approach 1:
Virtual partition cells act as intermediary structures between parent cells and child cells. They provide an additional layer of abstraction that mediates the relationship between large parent cells and their child cells, enabling finer-grained control over processing and memory management. The virtual partition cell handles the complexity of overlapping regions by providing a structured interface for verification tools to access and process specific portions of child cells independently.
3Ease of operation
If all cells are processed bottom-up in hierarchical manner, then the processing order is systematic, but the memory footprint increases and scalability is limited for increasingly larger designs
Solution Approach 1:
By segmenting parent cells into virtual partition cells, the patent enables the verification process to load and process only the necessary virtual partition cells into memory at any given time, rather than loading entire parent cells or the complete design hierarchy. This segmentation allows systematic bottom-up processing to continue while dramatically reducing memory footprint and improving scalability to increasingly larger designs.
Data Source
AI summary
Aspects described herein relate to physical verification of a design of an integrated circuit to be manufactured on a semiconductor die. One example method involves inserting a virtual partition cell in a parent cell of a layout of a design of an integrated circuit. A child cell of the parent cell has a first portion that overlaps the virtual partition cell and a second portion that is outside of the virtual partition cell. The method also includes creating, by one or more processors, a hierarchy of cells having the child cell and the virtual partition cell descending from the parent cell, wherein the child cell has multiple instances in the hierarchy of cells, and performing a design rule check runset on the parent cell based on the hierarchy.