Virtual Partitioning of Dense Algorithm Processing Unit for Real-Time Perception
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Solution Overview
Problem
Current integrated circuit architectures, particularly GPUs, lack the necessary processing capabilities to handle complex machine learning algorithms and sensor data processing tasks efficiently, leading to inefficiencies in real-time computing for autonomous robotics and vehicles.
Innovation Solution
A dense algorithm processing unit (DAPU) and perception processing unit (PPU) with a mesh architecture that includes multiple array cores, border cores, and a dispatcher, enabling in-memory computing and virtual partitioning of the integrated circuit for improved computational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If general purpose integrated circuits including CPUs and GPUs are used for sensor data processing, then the system can handle basic processing tasks, but the processing capabilities are insufficient for complex machine learning algorithms and real-time computing
Solution Approach 1:
The integrated circuit is divided into multiple array cores, each capable of independent processing. Each array core contains processing elements organized in a grid structure, allowing parallel execution of different portions of machine learning algorithms. This segmentation enables the system to handle complex computations by distributing work across multiple specialized units rather than relying on a single general-purpose processor.
Solution Approach 2:
The patent implements specialized processing elements within each array core that are optimized for specific computational tasks such as matrix multiplications and convolutions. Each processing element has locally integrated memory and computation units tailored for neural network operations, providing localized high-performance computing capabilities without requiring data to be fetched from distant memory locations.
2Adaptability or versatility
If additional and/or disparate circuitry is assembled to a traditional GPU to handle path planning and sensor fusion, then the perception processing needs are met, but the system becomes fragmented and inefficient
Solution Approach 1:
The array core architecture is designed to be universally applicable to multiple perception processing tasks including sensor fusion, object detection, classification, and path planning. The same array core infrastructure can be configured through software to execute different algorithms and data processing pipelines, eliminating the need for separate dedicated hardware circuits for each function.
Solution Approach 2:
The patent combines multiple perception processing functions into a single integrated circuit architecture. The array cores can simultaneously or sequentially execute different perception algorithms on different sensor data streams, merging what would traditionally require separate disparate circuits into one unified system that reduces fragmentation while maintaining versatility.
3Productivity
If data is fetched from memory during processing, then the system can access necessary information, but clock cycles are lost and computational efficiency is reduced
Solution Approach 1:
The patent implements a hierarchical memory structure where small on-chip memory units are nested within each processing element, which are nested within array cores, which are nested within the broader system memory. This nested architecture allows data to be cached at multiple levels, with the most frequently accessed data residing in the fastest memory locations closest to the processing units, minimizing the need to fetch data from distant memory and reducing clock cycle losses.
Data Source
AI summary
Systems and methods for virtually partitioning an integrated circuit may include identifying dimensional attributes of a target input dataset and selecting a data partitioning scheme from a plurality of distinct data partitioning schemes for the target input dataset based on the dimensional attributes of the target dataset and architectural attributes of an integrated circuit. The methods described herein may also include disintegrating the target dataset into a plurality of distinct subsets of data based on the selected data partitioning scheme and identifying a virtual processing core partitioning scheme from a plurality of distinct processing core partitioning schemes for an architecture of the integrated circuit based on the disintegration of the target input dataset. Additionally, the architecture of the integrated circuit may be virtually partitioned into a plurality of distinct partitions of processing cores and each of the plurality of distinct subsets of data may be mapped to one of the plurality of distinct partitions of processing cores.