Virtual Pattern Arrangement in Semiconductor Layout
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Solution Overview
Problem
Existing methods for arranging dummy patterns in semiconductor layouts struggle to effectively control the relative positions of virtual patterns and circuit patterns, leading to a low number of reserved virtual patterns and increased system resource usage, which hinders the improvement of iso-dense loading defects and design for reliability/manufacturability.
Innovation Solution
Defining a virtual pattern arrangement area on the semiconductor layout by setting forbidden areas based on minimum interval restrictions and selecting a positioning point at the boundary of this area to place virtual patterns, ensuring they meet the minimum interval requirements and avoid overlapping with circuit patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If dummy patterns are arranged using a single coordinate system with randomly selected origin, then the arrangement process is simple, but the relative position control between dummy patterns and circuit patterns is poor, resulting in many dummy patterns being deleted due to insufficient spacing
Solution Approach 1:
The patent divides the arrangement process into two independent stages: first arranging dummy patterns in iso regions using a single coordinate system, then arranging slot patterns in dense regions using a separate coordinate system. This segmentation allows each type of virtual pattern to be optimized independently, resolving the contradiction between operational simplicity and positioning precision.
Solution Approach 2:
The patent performs preliminary arrangement of dummy patterns in iso regions before finalizing the complete virtual pattern layout. By pre-positioning dummy patterns and establishing their coordinate system first, the subsequent arrangement of slot patterns can reference this established framework, improving overall position control while maintaining process simplicity.
2Reliability
If multiple dummy patterns are arranged to improve iso-dense loading defects, then the manufacturing reliability improves, but the system resource usage increases
Solution Approach 1:
The patent applies different arrangement strategies to different regions: dummy patterns are arranged in iso regions where uniformity is needed, while slot patterns are arranged in dense regions where spacing control is critical. This localized approach ensures reliability improvements are achieved efficiently by concentrating computational resources only where needed, rather than uniformly across the entire layout.
Solution Approach 2:
The patent arranges virtual patterns in two sequential passes rather than attempting to optimize all patterns simultaneously. This partial action approach processes dummy patterns first, then slot patterns, reducing the computational complexity of each individual arrangement operation while still achieving the cumulative reliability benefit of having both pattern types properly positioned.
3Manufacturing precision
If virtual patterns are added to improve process uniformity, then the manufacturing quality improves, but the risk of affecting lithography performance increases due to potential overlapping with circuit patterns
Solution Approach 1:
The patent introduces separate coordinate systems as intermediaries between the circuit pattern layout and the virtual pattern arrangement. By establishing distinct coordinate frameworks for dummy patterns and slot patterns, the system mediates the positioning process to ensure minimum spacing requirements are met, preventing harmful overlaps while maintaining process uniformity benefits.
Solution Approach 2:
The patent performs preliminary checks and arrangements to ensure virtual patterns meet minimum spacing requirements before finalizing the layout. By pre-positioning virtual patterns with proper spacing constraints applied, the system prevents lithography performance issues from occurring in the first place, rather than detecting and correcting them later.
Data Source
AI summary
A computer readable medium comprising multiple instructions stored in a computer readable device, upon executing these instructions, a computer performing the following steps: providing a first semiconductor layout and a second semiconductor layout predetermined to be fabricated on different material layers of a semiconductor device, the second semiconductor layout comprising a circuit pattern; setting a forbidden area of the circuit pattern on the first semiconductor layout according to a restriction condition; defining at least a virtual pattern arrangement area on a portion of the first semiconductor layout which does not correspond to the forbidden area; and selecting a positioning point at a boundary of the virtual pattern arrangement area and providing a virtual pattern array in the virtual pattern arrangement by taking the positioning point as an origin of a coordinate system of the virtual pattern array.