Virtual Per-Processor Timer Context Management

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Solution Overview

Problem

In multiprocessor systems, per-processor timers that are not always-on lose context during power transitions, requiring a shared platform timer to maintain system status, but this timer can only be controlled by one processor at a time, limiting independent power management across multiple processors.

Innovation Solution

A data structure in memory virtualizes a platform timer, allowing each processor to independently manage its timer by maintaining entries sorted by due time, enabling each processor to use a virtual per-processor timer derived from the platform timer, which is always on and maintains context through power transitions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If a per-processor timer is powered down during idle state, then power consumption is reduced, but the timer loses context and cannot maintain system status monitoring

Engineering Contradiction:

Improvepower consumptionVSAvoidcontext maintenance

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The system segments the timer functionality by creating a data structure that maintains separate timer entries for each processor, allowing individual processors to manage their own timer context independently while sharing the physical platform timer hardware

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system creates a virtual copy of the per-processor timer in software (data structure entry) that mirrors the functionality of a physical per-processor timer, allowing context to be preserved in memory even when the physical timer is powered down

Inventive Principle:

Principle #26Copying

2Use of energy by moving object

If a platform timer is shared among all processors, then power management is improved by allowing individual processors to power down their dedicated timers, but the platform timer can only be controlled by one processor at a time

Engineering Contradiction:

Improvepower management efficiencyVSAvoidtimer control accessibility

Core Design Contradiction:

Use of energy by moving objectVSEase of operation

Solution Approach 1:

The system introduces a data structure as an intermediary layer between processors and the platform timer, maintaining a sorted list of timer entries for multiple processors, allowing any processor to access and manage timer operations for any other processor without direct hardware control

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The platform timer is made universal by enabling any processor to program and control it for any processor's timing needs through the virtualization data structure, allowing the single physical timer to serve multiple processors simultaneously in different roles

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If a per-processor timer is always on to maintain context through power transitions, then context maintenance is ensured, but power consumption increases and independent power transitions cannot occur

Engineering Contradiction:

Improvecontext maintenanceVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The system creates a software copy of the timer context in the data structure that can be restored when needed, allowing the physical timer to be powered down while maintaining the ability to restore timing context through software

Inventive Principle:

Principle #26Copying

4Device complexity

If multiple processors share a single platform timer, then hardware resources are optimized, but the system cannot support independent power transitions for each processor

Engineering Contradiction:

Improvehardware resource optimizationVSAvoidindependent power transition capability

Core Design Contradiction:

Device complexityVSAdaptability or versatility

Solution Approach 1:

The system segments the timer management by maintaining separate data structure entries for each processor, allowing each processor to be managed independently in terms of power state and timing requirements while sharing the same physical hardware

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system adds a software/virtualization dimension to the hardware timer system, creating a layer of abstraction that enables independent control and power management for each processor while sharing the physical platform timer resource

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10534421B2Virtual per-processor timers for multiprocessor systems

Publication Date: 2020.01.14 MICROSOFT TECHNOLOGY LICENSING LLC

AI summary

A system provides virtual per-processor timers based on a timer such as a platform timer. To virtualize a timer to be used by each processor independently, a data structure is maintained in memory for the timer. The data structure has an entry for each interrupt to be produced for each processor using the timer, specifying the processor and the due time, with the entries sorted by due time. If the virtualized timer is a platform timer that maintains context during power transitions, a processor can switch to the virtual per-processor timer upon a context-losing power transition.