Virtual Physical Circuit for On-Chip Audio Communication
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Solution Overview
Problem
The proliferation of various audio interface standards, such as HDA, iDisp, I2S, DMIC, and DSPK, poses a significant burden for system developers who need to support and provide legacy support for these standards.
Innovation Solution
The implementation of a SoundWire based audio communication system that utilizes virtual physical (vPhy) circuits to convert SoundWire bus signaling format to an on-chip internal interface format, reducing the need for bi-directional signal lines and buffering, and allowing for more flexible placement of audio endpoints on the chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional audio interface standards (HDA, I2S, etc.) are used for on-chip communication, then compatibility with existing audio devices is maintained, but signaling complexity and timing control requirements increase
Solution Approach 1:
The patent introduces a SoundWire interface as an intermediary layer between the host processor and audio devices. This interface uses a simplified packet-based communication protocol that reduces signaling complexity compared to traditional standards like HDA or I2S, while maintaining compatibility with existing audio devices through protocol translation capabilities.
Solution Approach 2:
The patent changes the communication parameter from traditional bit-by-bit serial communication to packet-based communication with embedded timing information. This parameter change simplifies the timing control requirements by encoding timing data within the packets themselves, eliminating the need for complex external timing synchronization circuits.
2Productivity
If bi-directional signal lines are used for on-chip audio communication, then full-duplex communication is achieved, but the number of signal lines and device complexity increases
Solution Approach 1:
The patent achieves full-duplex communication by adding a time dimension to the communication protocol rather than requiring separate physical channels for each direction. The packet-based protocol allows simultaneous bidirectional data flow by multiplexing timing information within the data packets themselves, effectively utilizing the time domain to resolve the signal line constraint.
3Manufacturing precision
If buffering is implemented for timing synchronization, then timing accuracy is improved, but device complexity and cost increase
Solution Approach 1:
The patent replaces the mechanical/electronic buffering system with a software-based timing synchronization mechanism. Timing information is embedded in the communication packets, allowing the system to achieve precise timing synchronization through software control rather than requiring complex hardware buffers and timing circuits.
Data Source
AI summary
Techniques are provided for on-chip communication. A system implementing the techniques according to an embodiment includes a first virtual physical (vPhy) circuit couplable to a host through a vPhy interface and a second vPhy circuit couplable to a device, on the same chip as the host, through another vPhy interface. The system further includes a vPhy-to-vPhy interface between the vPhy circuits which includes signal lines to transmit a first data toggle signal from the first vPhy circuit to the second vPhy circuit, and a second data toggle signal from the second vPhy circuit to the first vPhy circuit. The first vPhy circuit is configured to generate the first data toggle signal based on a signal received from the host for transmission to the device. The second vPhy circuit is configured to generate the second data toggle signal based on signal received from the device for transmission to the host.