Virtual-Pixel Tessellation for CMOS TOF Precision

The patent applies binning by combining signals from multiple adjacent TOF pixels (e.g., 2x2 or larger groups) to form super-pixels. This merging approach increases the effective pixel size and electron capacity while maintaining high imaging resolution through the array of combined pixels, thereby resolving the contradiction between individual pixel precision and overall system resolution.

The patent segments the pixel array into multiple tap groups (e.g., quadruple-tap configuration with 4 separate readout paths) that can be independently controlled and read out. This segmentation allows selective binning of adjacent pixels with the same tap number while maintaining the ability to perform precise phase measurements through multiple taps, thus preserving both precision and resolution.

The patent implements a universal binning architecture where the same tap structure (e.g., quadruple-tap) is applied across all pixel groups, with standardized readout circuits and control logic. This multi-functional design allows the system to perform both individual pixel readout and binning operations using the same hardware framework, reducing configuration complexity while maintaining precision.

The patent pre-organizes adjacent pixels into fixed binning groups with predetermined tap assignments during the pixel array design phase. This preliminary structuring of pixel groups and their associated readout circuits simplifies the control logic and reduces runtime configuration complexity, making quadruple-tap binning achievable without significant system complexity.