Virtual Port Endpoint Logic for Multi-Protocol Integration
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Solution Overview
Problem
Traditional peripheral hub product designs are highly segmented due to varying requirements across different markets, making it difficult to integrate multiple intellectual property blocks on a single chip, leading to slow development of single chip system-on-chip (SoC) solutions that combine processor cores, memory controllers, and other acceleration elements.
Innovation Solution
The integration of a virtual downstream port with an integrated device fabric (IDF) and multi-function logic allows for efficient reuse of agents across platforms by removing the need for link and physical layers, enabling transparency to software and supporting plug-and-play functionality, while optimizing logic partitioning between agents and fabric.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional peripheral hub product designs are used with highly segmented architectures, then each market segment can have customized solutions, but the integration of multiple IP blocks on a single chip becomes difficult and development of SoC solutions slows down
Solution Approach 1:
The patent creates a universal interface architecture that can serve multiple market segments (server, desktop, mobile, embedded) through a single chip design. The interface logic is designed to be configurable and adaptable to different PCIe endpoint types (PCIe 2.0, PCIe 3.0, CXL 1.0, CXL 2.0, NVLink) without requiring separate dedicated hardware for each protocol, thus achieving multi-functionality that resolves the contradiction between customization and integration difficulty
2Reliability
If link and physical layers are included in the agent design, then complete PCIe functionality is achieved, but the design size, power consumption, and latency increase
Solution Approach 1:
The patent segments the PCIe interface functionality into two distinct parts: the agent (which implements only the transaction layer logic) and the interface logic (which implements the link and physical layers). This segmentation allows the agent to be lightweight and reusable across different platforms, while the interface logic handles the protocol-specific details. The agent can be integrated into various SoC designs without duplicating the heavy link and physical layer implementation, thus reducing design size and power consumption while maintaining complete PCIe functionality through the combined system
3Manufacturing precision
If agents are designed to be platform-specific, then optimal performance for each platform is achieved, but reuse of agents across various platforms becomes difficult
Solution Approach 1:
The patent introduces an intermediary interface logic layer that sits between the generic agent and the platform-specific requirements. This interface logic acts as a mediator that translates between the standardized agent interface and various platform-specific protocols (PCIe 2.0, PCIe 3.0, CXL 1.0, CXL 2.0, NVLink). The agent itself remains platform-agnostic and can be reused across different platforms, while the interface logic is customized for each platform to achieve optimal performance. This resolves the contradiction by separating platform-independent agent logic from platform-specific interface adaptations
Data Source
AI summary
In one embodiment, the present invention is directed to an integrated endpoint having a virtual port coupled between an upstream fabric and an integrated device fabric that includes a multi-function logic to handle various functions for one or more intellectual property (IP) blocks coupled to the integrated device fabric. The integrated device fabric has a primary channel to communicate data and command information between the IP block and the upstream fabric and a sideband channel to communicate sideband information between the IP block and the multi-function logic. Other embodiments are described and claimed.