Virtual Parallel Processing Unit Virtualization for Distributed Training Bottlenecks

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Solution Overview

Problem

Current methodologies for parallel/distributed training of deep neural networks face bottlenecks due to synchronization issues in minibatch stochastic gradient descent processing, particularly in host-accelerator communication, which limits bandwidth and efficiency in distributed computing systems.

Innovation Solution

The implementation of parallel processing unit virtualization and migration techniques, which involve determining virtual parallel processing units, generating routing tables, and mapping them to physical units, allowing for efficient data migration and communication link management across different physical processing units, optimizing communication patterns and reducing bottlenecks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If synchronized minibatch SDG processing is applied on distributed computing nodes, then parallel acceleration is achieved, but synchronization bottlenecks limit the overall process efficiency

Engineering Contradiction:
Improveparallel accelerationVSAvoidsynchronization bottleneck
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent segments the parallel processing system into virtual parallel processing units (vPPUs) that can be independently mapped to physical processing units. This segmentation allows different vPPUs to operate with different synchronization requirements, reducing the bottleneck effect of global synchronization while maintaining parallel acceleration benefits.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic mapping between vPPUs and physical PPU s, where the mapping can be changed during runtime based on workload characteristics and resource availability. This dynamic approach allows the system to adapt synchronization frequency and patterns, reducing unnecessary synchronization overhead while maintaining correctness.

Inventive Principle:
Principle #15Dynamics

2Reliability

If host-accelerator communication frequency is increased, then synchronization accuracy is improved, but bandwidth utilization decreases

Engineering Contradiction:
Improvesynchronization accuracyVSAvoidbandwidth utilization
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies different communication frequencies and synchronization patterns to different vPPU groups based on their specific computational patterns and data dependencies. This local quality approach ensures that only necessary synchronizations occur at high frequency, while other operations can proceed with lower communication overhead, improving bandwidth utilization without sacrificing required synchronization accuracy.

Inventive Principle:
Principle #3Local quality

3Adaptability or versatility

If virtual parallel processing units are mapped to physical units, then application migration capability is improved, but system complexity increases

Engineering Contradiction:
Improveapplication migration capabilityVSAvoidmapping management complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent introduces a virtualization layer with virtual parallel processing units that act as intermediaries between applications and physical processing units. This intermediary layer abstracts the complexity of physical PPU configurations and communication patterns, allowing applications to be migrated by simply remapping vPPUs to different physical PPU s without requiring application modification or complex manual reconfiguration.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Productivity

If ring-based implementation is used for All_Reduce function, then bandwidth utilization rate is improved, but communication overhead increases

Engineering Contradiction:
Improvebandwidth utilization rateVSAvoidcommunication overhead
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent implements partial ring-based All_Reduce operations where only the necessary subset of vPPUs participate in ring-based communication for each specific reduction operation. This partial action approach reduces the communication overhead compared to full ring-based implementation while maintaining the bandwidth utilization benefits for the required data aggregation tasks.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS12086654B2Parallel processing unit virtualization
Publication Date: 2024.09.10 T-HEAD (SHANGHAI) SEMICON CO LTD
  • US12086654B2 patent drawing
  • US12086654B2 patent drawing
  • US12086654B2 patent drawing

AI summary

Virtualization techniques can include determining virtual function routing tables for the virtual parallel processing units (PPUs) from a logical topology of a virtual function. A first mapping of the virtual PPUs to a first set of a plurality of physical PPUs can be generated. Virtualization can also include generating a first set of physical function routing tables for the first set of physical PPUs based on the virtual function tables and the first virtual PPU to physical PPU mapping. An application can be migrated from the first set of physical PPUs to a second set of PPUs by generating a second mapping of the virtual PPUs to a second set of a plurality of physical PPUs. A second set of physical function routing table for the second set of physical PPUs can also be generated based on the virtual function tables and the second virtual PPU to physical PPU mapping.