Virtual Probe Insertion for Side-Channel Leakage Detection

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Solution Overview

Problem

Current methods for detecting side channel attacks on devices like smartphones and credit cards are ineffective as they rely on post-manufacturing laboratory tests, which are costly and only address issues after IC fabrication, failing to protect against unintentional leakage of sensitive information through power supply noise, electromagnetic emission, and thermal emission.

Innovation Solution

The method involves using static timing analysis to identify and rank security-sensitive registers and nets within integrated circuits, inserting virtual probes at critical locations to measure power consumption and electromagnetic emissions, thereby detecting potential side channel leakage before manufacturing, and reducing computational complexity through selective probing and parallel processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If post-manufacturing laboratory tests are used to detect side channel attacks, then detection capability is achieved, but cost and time consumption increase significantly

Engineering Contradiction:
Improvedetection capabilityVSAvoidtesting time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent performs side channel analysis during the IC design phase using static timing analysis and power consumption simulation, rather than waiting for post-manufacturing testing. This preliminary action identifies security-sensitive registers and nets before fabrication, allowing designers to mitigate vulnerabilities in the design itself, thereby eliminating the need for costly and time-consuming post-manufacturing laboratory tests while maintaining detection capability

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If comprehensive side channel emission analysis is performed at multiple locations, then detection accuracy improves, but computational complexity increases

Engineering Contradiction:
Improvedetection accuracyVSAvoidcomputational complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent extracts and focuses analysis only on security-sensitive registers and nets by using static timing analysis to trace information flow from cryptographic operations. Instead of performing comprehensive analysis at all locations, the methodology identifies and isolates the specific circuits that actually process secret data, thereby maintaining detection accuracy while significantly reducing computational complexity by eliminating analysis of non-critical circuits

Inventive Principle:
Principle #2Taking out (Extraction)

3Measurement precision

If static timing analysis is used to identify security-sensitive circuits, then analysis precision improves, but processing speed decreases due to path explosion

Engineering Contradiction:
Improveanalysis precisionVSAvoidprocessing speed
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent segments the IC circuit into distinct functional blocks and uses static timing analysis to trace information flow within each segment separately. By dividing the large-scale circuit analysis into smaller, manageable segments and using parallel processing for different segments, the methodology maintains precise identification of security-sensitive circuits while avoiding the path explosion problem that would occur with monolithic analysis of the entire circuit

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11599633B1Security information extraction and probe insertion for side-channel analysis
Publication Date: 2023.03.07 ANSYS INC
  • US11599633B1 patent drawing
  • US11599633B1 patent drawing
  • US11599633B1 patent drawing

AI summary

Methods, machine readable media and systems for performing side channel analysis are described. In one embodiment, a method can determine, from a gate level representation of a circuit in a layout on a die of an IC, a first set of paths through the circuit that process security related data during operation of the circuit, the circuit including a second set of paths that do not process security related data; and the method can further determine, in a simulation of power consumption in the first set of paths but not the second set of paths, power consumption values in the first set of paths to determine potential security leakage of the security related data in the circuit. The method can further determine, from the power consumption values, positions in the layout for inserting virtual probes on the die for use in measuring security metrics that indicate potential leakage of the security related data. The insertion of the virtual probes is relative to the actual simulated layout of the die. Other methods, machine readable media and systems are also described.