Virtual Probe Sequencing for Dynamic Circuit Debugging
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Solution Overview
Problem
As electronic circuit cards and assemblies become more complex and miniaturized, physically probing internal nets becomes increasingly difficult, especially when using traditional methods like oscilloscope or logic analyzer probes, due to the challenges of accessing densely packed pins or ball grid arrays, making it hard to acquire logic states and transition timings during dynamic functional stimulation.
Innovation Solution
A digital circuit electronic system that includes a JTAG device in communication with a JTAG interface, using a dynamic functional interface and electronic equipment with algorithms to virtually probe pins by controlling the timing of the JTAG TCK rising clock edge to trigger a JTAG SAMPLE command during dynamic functional stimulation, capturing and storing logic states of the pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Difficulty of detecting and measuring
If physical probing methods (oscilloscope probe, logic analyzer probe) are used to access internal nets, then diagnostic fault isolation and debugging capability is improved, but physical access becomes increasingly difficult due to increased circuit complexity and miniaturization
Solution Approach 1:
The patent creates a virtual copy of the physical probing function through JTAG boundary scan. Instead of physically connecting probes to internal nets, the system uses JTAG test access ports to virtually access and probe internal circuit nodes. The JTAG algorithm emulates the probing function by shifting test patterns through the boundary scan register, allowing diagnostic measurements without physical contact with internal circuit points.
Solution Approach 2:
The patent introduces JTAG interface as an intermediary between the testing equipment and the internal circuit nets. The JTAG boundary scan mechanism serves as a mediator that provides a standardized test access path through the circuit's existing JTAG test access ports, enabling indirect measurement of internal nodes without requiring direct physical access to densely packed or inaccessible pins.
2Ease of operation
If JTAG boundary scan is used to probe internal nets, then physical access requirement is reduced, but capturing logic states during dynamic functional stimulation requires precise timing control of JTAG TCK rising clock edge
Solution Approach 1:
The patent performs preliminary actions by pre-configuring the JTAG SAMPLE command in the boundary scan register before the actual sampling moment. The test pattern and sampling timing are prepared in advance through the JTAG programming sequence, allowing the precise timing control to be executed automatically when the TCK rising edge occurs during dynamic functional stimulation, without requiring manual timing adjustment.
Solution Approach 2:
The patent implements feedback mechanisms through the JTAG shift out operation, where captured sample data is shifted out and made available for analysis. The system can compare captured logic states against expected values and provide feedback on circuit functionality during dynamic operation, enabling real-time verification of timing-critical behaviors.
3Area of moving object
If densely packed pins or ball grid arrays are used to increase circuit density, then miniaturization is achieved, but physical probing becomes problematic
Solution Approach 1:
The patent replaces the need for physical probe contact with a virtual probing mechanism. The JTAG boundary scan creates a digital copy of the probing function by shifting test patterns through the boundary scan register and capturing logic states electronically. This virtual approach eliminates the mechanical challenges of physically accessing densely packed pins or BGA balls while maintaining full diagnostic capability.
Solution Approach 2:
The patent makes the JTAG test access ports universal by enabling them to serve multiple functions: boundary scan probing, logic state capture during dynamic stimulation, and timing-critical measurement. This multi-functional use of the JTAG interface replaces the need for separate physical probing mechanisms, allowing a single interface to access any internal net regardless of physical accessibility.
Data Source
AI summary
An internal net of a digital circuit is virtually probed while performing a dynamic functional stimulation that includes changing vectors asserted to a dynamic functional interface. A JTAG SAMPLE command is triggered through a JTAG interface at a timing during the dynamic functional stimulation by controlling the timing of a JTAG TCK rising clock edge. Captured JTAG SAMPLE data is shifted out to the JTAG interface. The JTAG SAMPLE data, which includes the logic states of internal nets at a chosen timing during the dynamic functional stimulation, are stored. A sequence database is built by repeating the test with incrementally different JTAG rising clock edge timings.