Virtual Processor Memory Access via Hardware Comparator

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Solution Overview

Problem

Existing systems face challenges in securely sharing memory between processors and virtual processing elements, leading to potential corruption of data due to lack of coordination and security vulnerabilities from malicious software.

Innovation Solution

A system that uses a comparator to grant access to memory locations based on virtual processing element identification, with an access list instantiated in hardware to prevent unauthorized access, ensuring secure read and write operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If memory is shared between processors and virtual processing elements without coordination mechanisms, then memory access speed is improved, but data corruption occurs due to lack of synchronization

Engineering Contradiction:
Improvememory access speedVSAvoiddata integrity
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent introduces a memory management unit (MMU) as an intermediary component that mediates all memory access requests from multiple virtual processing elements. The MMU maintains an access list that tracks which virtual processing elements are authorized to access specific memory regions, and it enforces access control by comparing the requesting virtual processing element's identity against the access list before granting memory access. This intermediary mechanism enables fast concurrent access while preventing data corruption through centralized authorization control.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If access control mechanisms are implemented to prevent unauthorized memory access, then security is improved, but system overhead increases due to additional signaling and coordination

Engineering Contradiction:
Improvememory securityVSAvoidsystem overhead
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements preliminary action by pre-configuring an access list in the memory management unit that specifies which virtual processing elements are authorized to access which memory regions. This access list is established before runtime operations, allowing the system to make rapid authorization decisions during execution without requiring complex runtime negotiation or signaling between virtual processing elements. The pre-established access rules enable secure memory access with minimal overhead during actual operations.

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If software-managed memory allocation is used, then flexibility is improved, but security vulnerabilities arise from malicious software that can access unauthorized memory locations

Engineering Contradiction:
Improvememory allocation flexibilityVSAvoidmalicious software access
Core Design Contradiction:
Adaptability or versatilityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces a hardware-based memory management unit as an intermediary between software and physical memory. This MMU maintains a protected access list that software cannot modify, and it enforces memory access control by verifying each memory access request against the access list. This hardware intermediary prevents malicious software from accessing unauthorized memory locations while still allowing legitimate software to allocate and manage memory flexibly according to the authorized access patterns defined in the access list.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8024539B2Virtual processor based security for on-chip memory, and applications thereof
Publication Date: 2011.09.20 ARM FINANCE OVERSEAS LTD
  • US8024539B2 patent drawing
  • US8024539B2 patent drawing
  • US8024539B2 patent drawing

AI summary

A processor-based method, system and apparatus to comprise a method, system and apparatus to access a memory location in an on-chip memory based on a virtual processing element identification associated with an instruction. The system comprises multiple virtual processing elements, an access list and a comparator coupled to the memory and the access list. In response to an instruction from a virtual processing element to access a memory location in the memory, the comparator compares a first virtual processing identification associated with the instruction to a second virtual processing identification stored in the access list and grants access to the virtual processing element that generated the instruction to read from or write to the memory location if the first virtual processing element identification is equal to the second virtual processing element identification. The data in the memory is allocated and de-allocated by software.