Virtual Prototype Partitioning for Parallel Hardware Simulation
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Solution Overview
Problem
Virtual prototypes used in SoC design simulations often lack sufficient speed for software development while requiring accurate analysis of hardware behavior, with loosely-timed models executing quickly but lacking timing detail and cycle-accurate models executing too slowly for practical use.
Innovation Solution
The method involves partitioning a virtual prototype simulation into autonomous execution segments, creating checkpoints, and executing these segments in parallel to achieve faster execution times, with each segment sharing similar lengths to enhance simulation speed without compromising accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a cycle-accurate virtual prototype model is used to maintain timing accuracy, then the timing precision is improved, but the execution speed deteriorates significantly
Solution Approach 1:
The virtual prototype simulation is divided into multiple autonomous execution segments that can be executed in parallel. Each segment represents a discrete portion of the overall simulation with defined start and end points, allowing independent execution while maintaining the timing accuracy of cycle-accurate models within each segment.
Solution Approach 2:
The patent transitions from single-threaded sequential execution to multi-threaded parallel execution by introducing temporal and spatial dimensions. Multiple execution segments run simultaneously across different processor cores, transforming the execution model from one-dimensional sequential processing to multi-dimensional parallel processing.
2Speed
If a loosely-timed virtual prototype model is used to achieve faster execution, then the execution speed is improved, but the timing detail is lost
Solution Approach 1:
Different portions of the virtual prototype simulation are executed at different levels of timing accuracy. Within each autonomous execution segment, cycle-accurate timing detail is maintained locally, while the overall system achieves faster execution through parallelization. Each segment can be configured with appropriate timing accuracy based on local requirements.
3Device complexity
If the virtual prototype simulation is executed linearly in a single thread, then the implementation is simple, but the execution time is excessively long
Solution Approach 1:
Before executing the parallel simulation, the patent performs preliminary actions including: (1) identifying suitable breakpoints in the simulation code where autonomous segments can be created, (2) creating checkpoint data structures to store segment boundaries and synchronization points, and (3) configuring execution parameters for each segment. This preparation enables efficient parallel execution without requiring complex modifications to the core simulation logic.
4Speed
If the virtual prototype is partitioned into multiple autonomous execution segments for parallel processing, then the execution speed is improved significantly, but the system complexity increases
Solution Approach 1:
The patent implements feedback mechanisms where checkpoint data from previously executed segments is used to initialize and configure subsequent segments. Execution results and timing information from each segment feed back into the coordination system, which adjusts segment boundaries and synchronization points to optimize parallel execution efficiency while managing system complexity.
Data Source
AI summary
A method including accessing a first virtual prototype configured to perform a first simulation of a hardware design, identifying checkpoints within the first virtual prototype, each checkpoint including a storage state and/or behavioral state, and determining breakpoints for dividing execution of a second virtual prototype into a series of execution segments, where the second virtual prototype is configured to perform a second simulation of the hardware design, the second virtual prototype includes virtual models representing a separate portion of the hardware design, each virtual model representing a same portion of the hardware design as a corresponding virtual model of the first virtual prototype. The method may include mapping the storage state and/or behavioral state of each checkpoint to a respective execution segment, executing the second simulation while collecting respective data regarding execution of each execution segment, where two or more execution segments are executed concurrently, and aggregating the respective data.