Virtual Power Rail Feedback Control for IC Leakage Reduction
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Solution Overview
Problem
As integrated circuits shrink, leakage current increases, making it difficult to reduce power consumption during retention mode without compromising restart times or risking data loss due to low voltage levels.
Innovation Solution
The implementation of operational mode transistors with adaptive retention mode control, utilizing a control voltage to maintain a predetermined virtual rail voltage through a closed-loop feedback mechanism, ensuring sufficient voltage difference and reducing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If header and footer transistors are used to isolate virtual power rails during retention mode, then leakage current is reduced, but restart time increases and data loss risk increases due to low voltage levels
Solution Approach 1:
The patent applies dynamics by making the transistor isolation state adjustable rather than fixed. The first transistors can be dynamically switched between fully isolating (retention mode) and partially conductive (restart mode) states, allowing the system to adapt its power isolation level based on operational requirements. This resolves the contradiction by enabling both deep isolation for low leakage and partial conduction for fast restart.
Solution Approach 2:
The patent changes the voltage parameter applied to the first transistors. During retention mode, a first voltage level is applied to maximize isolation and minimize leakage. During restart mode, a second voltage level is applied to reduce isolation and enable faster voltage recovery on virtual power rails. This parameter adjustment directly addresses both the leakage reduction and restart time requirements.
2Loss of energy
If voltage difference on virtual rails is reduced during retention mode, then leakage current decreases, but functional circuits may dip too low resulting in data loss
Solution Approach 1:
The patent introduces second transistors as intermediary elements between the virtual power rails and ground. These transistors provide a controlled leakage path that prevents the virtual rail voltage from dropping too low, thereby maintaining data integrity. The second transistors act as mediators that balance the isolation requirement with the minimum voltage requirement for reliable data retention.
Solution Approach 2:
The patent employs feedback mechanisms where control circuitry monitors the voltage levels on virtual power rails and adjusts the control signals to the first and second transistors accordingly. This feedback ensures that the voltage difference is reduced sufficiently to minimize leakage while maintaining the minimum voltage threshold required for data retention reliability.
3Productivity
If header and footer transistors supply power to virtual power rail, then functional circuits can operate, but power consumption increases during retention mode
Solution Approach 1:
The patent segments the power supply function by separating the roles of first transistors (isolation control) and second transistors (leakage path control). This segmentation allows independent optimization of each transistor's operation - the first transistors can provide strong isolation to reduce leakage, while the second transistors maintain minimal conduction to support functional circuits, achieving both low power consumption and operational capability.
Data Source
AI summary
An integrated circuit is provided with operational mode header transistors which connect a virtual power rail to a VDD power supply. A controller circuit, responsive to a sensed voltage signal from a voltage sensor which reads the virtual rail voltage VVDD, generates a control signal which controls the operational mode transistors. The control signal is derived from an interface voltage power supply that provides higher voltage VDD IO than the VDD power supply and thus able to overdrive the operational mode transistors via either a gate bias voltage or a bulk bias voltage. The amount of leakage through the operational mode transistors is controlled in a closed loop feedback arrangement so as to maintain a predetermined target value or range for the virtual rail voltage. The operational mode transistor may also be controlled to support dynamic voltage and frequency scaling.