Virtual Memory Rank Grouping for 3D DRAM Signal Alignment
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Solution Overview
Problem
Signal misalignment and thermal variations between memory channels in three-dimensionally stacked DRAM dies lead to increased memory errors due to variations in process, voltage, and temperature, causing bit flip errors and reduced effective margin eyes.
Innovation Solution
Grouping memory devices into virtual memory ranks based on electrical and thermal characteristics, using adjustable delay circuits to align command and address signals, and implementing memory calibration algorithms to enhance electrical reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory devices are grouped into virtual memory ranks based on electrical and thermal characteristics, then memory errors are reduced and electrical margins are enhanced, but device complexity and manufacturing complexity increase
Solution Approach 1:
The patent segments memory devices into multiple virtual memory ranks based on their electrical and thermal characteristics. Each virtual rank groups devices with similar characteristics, allowing independent optimization and control of each group. This segmentation reduces memory errors by ensuring that devices operating under similar conditions are managed together, while the complexity is managed through systematic grouping criteria.
Solution Approach 2:
The patent changes the organizational parameter of memory devices from physical stacking order to electrical and thermal characteristic-based grouping. By using adjustable delay circuits to compensate for signal skew and creating virtual ranks based on measured characteristics, the system transforms the memory organization from a fixed physical structure to a flexible logical structure that optimizes for reliability.
2Reliability
If adjustable delay circuits are used to align command and address signals, then signal misalignment is reduced and memory errors decrease, but device complexity and power consumption increase
Solution Approach 1:
The patent implements preliminary calibration procedures that measure signal skew between command and address paths before normal operation. Adjustable delay circuits are configured in advance based on these measurements to pre-compensate for misalignment. This preliminary action ensures that signals are properly aligned during subsequent memory operations without requiring continuous complex control during runtime.
Solution Approach 2:
The system uses feedback from calibration procedures to automatically adjust delay circuit settings. During initial calibration, the system measures actual signal arrival times and uses this feedback to configure the adjustable delay circuits optimally. This feedback mechanism allows the system to adapt to manufacturing variations and ensure proper signal alignment without manual intervention.
3Reliability
If memory devices are grouped by thermal characteristics, then thermal variations are compensated and memory reliability improves, but measurement precision requirements and calibration time increase
Solution Approach 1:
The patent implements self-service thermal characterization where the memory devices themselves provide information about their thermal characteristics during normal operation. By monitoring error rates and performance metrics under different operating conditions, the system infers thermal characteristics without requiring external thermal measurement equipment. This approach reduces measurement precision requirements while still enabling effective thermal-based grouping.
Solution Approach 2:
The system performs preliminary thermal characterization during manufacturing or initial setup by measuring device behavior under controlled temperature conditions. These preliminary measurements establish baseline thermal characteristics that are stored and used for subsequent virtual rank assignments. This preliminary action reduces the need for continuous precise thermal measurements during operation.
Data Source
AI summary
A memory system includes a first set of memory devices, a second set of memory devices, and a memory controller circuit system. The memory controller circuit system groups a first one of the memory devices in each of the first and the second sets into a first virtual memory rank based on eye margins of first data signals sampled by the first virtual memory rank. The memory controller circuit system groups a second one of the memory devices in each of the first and the second sets into a second virtual memory rank based on eye margins of second data signals sampled by the second virtual memory rank. The memory controller circuit system accesses the memory devices in the first virtual memory rank separately from the memory devices in the second virtual memory rank during data access operations.