Virtual Register Chain for Clock Skew Mitigation in IC Pipelines
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Solution Overview
Problem
Synchronous pipeline registers in integrated circuits are limited by clock skew issues, which hinder increased clock speed and throughput, while designing with asynchronous interconnection elements is challenging due to unfamiliarity with asynchronous designs among engineers.
Innovation Solution
The integration of synchronous elements connected by asynchronous routing elements, where intermediate registers are replaced with virtual registers and asynchronous handshaking elements, allowing data to be conveyed between source and destination registers through asynchronous interconnection, with control signals delayed to maintain equivalent behavior.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If synchronous pipeline registers are used to increase throughput, then the throughput of signals is improved, but clock skew issues arise which limit the amount by which clock speed can be increased
Solution Approach 1:
The patent introduces asynchronous routing elements as intermediaries between synchronous pipeline registers. These asynchronous elements act as mediators that transfer data between synchronous stages without being constrained by clock skew, thereby maintaining throughput improvements while eliminating the reliability issues associated with high-speed clocking
Solution Approach 2:
The patent segments the synchronous pipeline into stages connected by asynchronous interconnection elements. This segmentation allows the synchronous registers to operate at their optimal speeds while the asynchronous segments handle the data transfer, isolating the system from clock skew limitations
2Productivity
If asynchronous interconnection elements are used to convey signals, then throughput can be increased without clock skew limitations, but design complexity increases and engineers face unfamiliarity with asynchronous designs
Solution Approach 1:
The patent merges synchronous and asynchronous design paradigms into a hybrid architecture. Synchronous pipeline registers are combined with asynchronous routing elements, allowing the benefits of both approaches: the ease of synchronous design for data processing and the high throughput of asynchronous communication for data transfer
Solution Approach 2:
The patent creates a universal design framework that can handle both synchronous and asynchronous operations. The system can operate in synchronous mode for compatibility with existing designs and switch to asynchronous mode for performance-critical paths, providing multi-functionality that accommodates different design skill levels and performance requirements
Data Source
AI summary
Integrated circuits may include synchronous nodes and asynchronous routing elements coupled between the synchronous nodes. A synchronous design implemented in such an integrated circuit may identify a register chain having a source register, a destination register, and intermediate registers. A virtual register may be created for each of the intermediate registers, which may then be removed from the synchronous design. The created virtual registers may be connected in series to form a virtual register chain between the source and destination registers. Each of the created virtual registers may be assigned to an asynchronous routing element that connects the source and destination registers on the integrated circuit. EDA tools such as viewers or a timing analysis tool may be configured to display the virtual registers instead of the asynchronous interconnection elements.