3D Virtual Semiconductor Fabrication Pattern Dependent Effects
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Solution Overview
Problem
Current semiconductor fabrication processes face challenges in accurately modeling pattern-dependent effects, which are crucial for predicting device structures due to the complexity of advanced technology nodes, leading to increased costs and duration in experimental methodologies.
Innovation Solution
A 3-D Virtual Semiconductor Fabrication Environment generates a local mask from a 3-D model and combines it with a global mask, using proximity functions to create a loading map that modifies process behavior, enabling more accurate prediction of device structures by accounting for pattern density, feature size, and aspect ratio dependencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If trial-and-error physical experimentation is used to develop fabrication processes, then process development can be performed with simple modeling approaches, but the cost and duration of development increase significantly
Solution Approach 1:
The patent creates a virtual copy of the semiconductor fabrication process by generating a 3-D structural model that replicates the physical fabrication environment. This virtual model allows process development and optimization to be performed digitally, eliminating the need for repeated physical experimentation while maintaining high modeling accuracy for pattern-dependent effects
Solution Approach 2:
The system performs preliminary virtual fabrication runs to identify and model pattern-dependent effects before actual physical fabrication. By pre-characterizing these effects through computational modeling and storing them in a library, the system avoids time-consuming trial-and-error experimentation during physical process development
2Manufacturing precision
If detailed 3-D modeling of pattern dependent effects is implemented, then prediction accuracy of device structures improves, but computational complexity increases
Solution Approach 1:
The patent segments the complex fabrication process into discrete pattern-dependent effects, each modeled separately and stored in a library. By dividing the overall process into manageable components (different etching effects, deposition effects, etc.), the system achieves high prediction accuracy without overwhelming computational complexity
Solution Approach 2:
The system uses parameter-based modeling where pattern-dependent effects are characterized by key parameters (pattern density, feature size, aspect ratio) rather than full geometric modeling. This approach maintains high prediction accuracy while significantly reducing computational complexity through parameterization
3Loss of energy
If virtual fabrication modeling is used instead of physical experimentation, then development cost decreases, but modeling of pattern dependent effects becomes more challenging
Solution Approach 1:
The system performs preliminary virtual experimentation to build a library of pattern-dependent effects before production use. This upfront computational investment creates reusable models that can be applied to multiple fabrication scenarios, reducing overall development costs while managing modeling complexity through systematic characterization
Solution Approach 2:
The patent introduces an intermediary layer between virtual modeling and physical fabrication - a library of pre-characterized pattern-dependent effects. This intermediary allows the virtual fabrication environment to accurately represent complex physical phenomena without requiring direct complex physics-based simulations for each process step
Data Source
AI summary
Improving semiconductor device fabrication by enabling the identification and modeling of pattern dependent effects of fabrication processes is discussed. In one embodiment a local mask is generated from a 3-D model of a semiconductor device structure that was created in a 3-D virtual semiconductor fabrication environment from 2-D design layout data and a fabrication process sequence. The local mask is combined with a global mask based on the original design layout data to create a combined mask. The combined mask is convolved with at least one proximity function to generate a loading map which may be used to modify the behavior of one or more processes in the process sequence. This behavior modification enables the 3-D virtual semiconductor fabrication environment to deliver more accurate 3-D models that better predict the 3-D device structure when performing the virtual semiconductor device fabrication that serves as a prelude to physical fabrication.