Virtual Spacers for Leakage Control in Semiconductor Devices
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Solution Overview
Problem
Semiconductor devices with inadequate spacer widths experience increased gate-induced drain leakage (GIDL) and variation in leakage current (IOFF) when operating at higher voltages, due to the reduction in spacer width with device size reduction.
Innovation Solution
The introduction of virtual spacers made of the same material as the dielectric layer, positioned between the gate conductive layer and the spacers, increases the distance between the contact hole and the gate conductive layer, allowing transistors to meet required operating voltages while being compatible with existing processes and avoiding leakage issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the spacer width is reduced to match device size reduction, then device density is improved, but gate-induced drain leakage (GIDL) increases and leakage current variation increases
Solution Approach 1:
The invention divides the spacer structure into two segments: a first spacer formed directly on the gate electrode with a first width, and a second spacer formed on the first spacer with a second width. This segmentation allows each spacer to serve different functions - the first spacer provides basic isolation while the second spacer provides the necessary width for high-voltage devices to control leakage current, thus resolving the contradiction between device density and leakage current control.
Solution Approach 2:
The invention applies different spacer widths to different regions: narrower spacers for low-voltage devices and wider spacers for high-voltage devices. This local quality approach allows each device type to have the optimal spacer width for its operating conditions, preventing GIDL in high-voltage devices while maintaining high device density overall.
2Ease of manufacture
If a single spacer width is used for all devices, then manufacturing process is simplified, but high-voltage devices experience increased GIDL and leakage current variation
Solution Approach 1:
The spacer formation process is segmented into two sequential steps: forming the first spacer followed by forming the second spacer. This segmented approach enables different spacer widths for different device regions while using a unified manufacturing process flow, thus maintaining ease of manufacture while achieving the reliability needed for high-voltage devices.
Solution Approach 2:
The first spacer is formed as a preliminary structure before forming the second spacer. This preliminary action creates a foundation that allows the second spacer to be formed with precise width control for high-voltage devices, ensuring proper leakage current control while maintaining process simplicity through a sequential formation approach.
3Reliability
If the spacer width is increased for high-voltage devices, then GIDL is reduced, but device density decreases
Solution Approach 1:
The invention implements local quality by providing wider second spacers specifically for high-voltage devices to control GIDL, while low-voltage devices can utilize the narrower first spacers. This localized differentiation ensures proper GIDL control where needed without unnecessarily reducing device density across all devices.
Solution Approach 2:
The dual-spacer structure segments the isolation function: the first spacer provides baseline isolation for all devices, while the second spacer provides additional width specifically for high-voltage devices. This segmentation allows high-voltage devices to achieve proper GIDL control with wider effective spacer width while low-voltage devices maintain higher density with narrower spacers.
Data Source
AI summary
A method of fabricating a semiconductor device includes: forming a first transistor including: forming a plurality of lightly doped regions in a substrate; forming a first gate structure on the substrate, the first gate structure covering portions of the plurality of lightly doped regions and a portion of the substrate; forming first spacers on sidewalls of the first gate structure; forming doped region in the lightly doped regions; forming an etching stop layer on the substrate; patterning the etching stop layer and the first gate structure to form a second gate structure, and to form a plurality of trenches between the second gate structure and the first spacers; and forming a first dielectric layer on the substrate to cover the etching stop layer and fill the plurality of trenches. The first dielectric layer filled in the trenches is used as virtual spacers.