Virtual Spanning Tree Global Clock Distribution

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Solution Overview

Problem

Existing multiprocessor systems require a dedicated separate virtual channel to maintain a global clock, which leads to queuing delays and interference with application programs, and lacks flexibility in handling node or link failures.

Innovation Solution

A method using a virtual spanning tree with memory-mapped control registers to propagate a global clock signal through a multiprocessor system, where each node can act as a root and generate its own clock if necessary, eliminating the need for additional physical networking hardware and allowing the system to tolerate node or link failures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a dedicated separate virtual channel is used to maintain global clock, then clock synchronization is achieved, but queuing delays occur and application program performance deteriorates

Engineering Contradiction:
Improveclock synchronizationVSAvoidapplication program performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent merges the global clock signal transmission with existing network fabric channels by piggybacking clock signals on data packets. The root node injects global clock signals into the network fabric, which then traverse the same physical infrastructure used for data communication, eliminating the need for dedicated virtual channels and avoiding additional queuing delays.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The network fabric channels are made multi-functional by serving both data transmission and global clock distribution purposes. The same physical network infrastructure that handles application data traffic is also utilized to propagate synchronization signals throughout the multiprocessor system, maximizing resource utilization.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If iterative data collection and calculation is used to maintain time deltas, then common timescale is maintained, but system complexity increases

Engineering Contradiction:
Improvecommon timescaleVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The root node pre-calculates and distributes global clock signals to all child nodes before timing-critical operations occur. Each node receives advance notification of clock events through the distributed signals, eliminating the need for iterative measurement and calculation of time deltas during runtime.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The root node acts as an intermediary that centralizes the clock synchronization function. Instead of having each node pair iteratively measure and calculate time deltas with multiple peers, the root node serves as a single point of reference that distributes synchronized timing information to all nodes in the system.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If separate virtual channel is allocated for clock management, then clock distribution is enabled, but network resource utilization decreases

Engineering Contradiction:
Improveclock distributionVSAvoidnetwork resource utilization
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent combines clock distribution traffic with data traffic in the same network channels. By piggybacking global clock signals on existing data packets and utilizing the same physical infrastructure, the system maximizes network resource utilization while maintaining reliable clock distribution.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS8239704B2Global clock via embedded spanning tree
Publication Date: 2012.08.07 CRAY INC
  • US8239704B2 patent drawing
  • US8239704B2 patent drawing
  • US8239704B2 patent drawing

AI summary

In some embodiments, the present invention relates to a method of maintaining a global clock within a multiprocessor system having a plurality of nodes that are connected in a network via links. A virtual spanning tree is mapped onto the network and the nodes and the links are configured such that each node is in a parent-child relationship with one or more other nodes in the virtual spanning tree. A global clock is generated in a root of the virtual spanning tree and global clock signals are communicated down the virtual spanning tree to each of the nodes.