Virtual Switch Packet Routing via Direct Memory Access

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Solution Overview

Problem

Current techniques for packet classification and transmission in virtualized environments, such as VMDQ, require multiple copy operations, leading to resource inefficiencies and latency, especially with increasing packet sizes or transactions, and do not support live migration or virtual switching techniques like Open vSwitch.

Innovation Solution

Implementing a direct memory access (DMA) operation to transfer packet headers, payloads, and descriptors directly from a network interface to a virtual machine's queue without intermediate buffers, using a virtual switch to manage routing rules based on packet properties like IP addresses, thereby reducing copy operations and enhancing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple copy operations are used to transfer packets from network interface to VM queue, then packet transmission can be achieved with existing virtualization techniques, but CPU usage increases and latency increases

Engineering Contradiction:
Improvepacket transmission capabilityVSAvoidCPU usage efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent extracts the packet data from the network interface and writes it directly to the VM queue buffer in memory, eliminating the intermediate copy operations through direct memory access (DMA). This removes the redundant copying steps that consume CPU resources while maintaining reliable packet transmission.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a descriptor structure as an intermediary that contains buffer information and routing rules. This descriptor enables the network interface to directly access and write packet data to the correct VM queue buffer without requiring multiple copy operations, thus reducing CPU usage while maintaining transmission reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If multiple copy operations are used to transfer packets, then packet transmission can be achieved, but latency increases especially with increasing packet sizes

Engineering Contradiction:
Improvepacket transmission capabilityVSAvoidpacket transmission latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts packet data directly from the network interface and writes it in a single operation to the VM queue buffer, eliminating multiple copy operations. This single direct write operation significantly reduces transmission latency, especially for larger packet sizes where multiple copies would otherwise be required.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent performs preliminary setup by programming the network interface with routing rules and buffer information in descriptors before packet arrival. This preliminary configuration enables direct packet routing without intermediate processing, reducing latency while maintaining reliable transmission.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If intermediate buffers are used for packet copying, then packet transmission can be achieved with existing techniques, but memory resources are wasted and efficiency decreases

Engineering Contradiction:
Improvepacket transmission capabilityVSAvoidmemory resource utilization
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent eliminates the need for intermediate buffers by extracting packet data directly from the network interface and writing it to the final VM queue buffer location. This direct memory access approach removes redundant buffer allocations, improving memory resource utilization while maintaining transmission reliability.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent makes the VM queue buffer serve multiple functions: it acts as both the destination for packet data and the storage location accessible by the VM. This eliminates the need for separate intermediate buffers, optimizing memory resource utilization while maintaining reliable packet transmission.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11487567B2Techniques for network packet classification, transmission and receipt
Publication Date: 2022.11.01 INTEL CORP
  • US11487567B2 patent drawing
  • US11487567B2 patent drawing
  • US11487567B2 patent drawing

AI summary

A virtual machine (VM) can provision a region of memory for a queue to receive packet header, packet payload, and/or descriptors from the network interface. A virtual switch can provide a routing rule to a network interface to route a received packet header, packet payload, and/or descriptors associated with the VM to the provisioned queue. A direct memory access (DMA) transfer operation can be used to copy the received packet header, packet payload, and/or descriptors associated with the VM from the network interface to the provisioned queue without copying the packet header or payload to an intermediate buffer and from the intermediate buffer to the provisioned queue. A DMA operation can be used to transfer a packet or its descriptor from the provisioned queue to the network interface for transmission.