Virtual Timer Interrupt Coalescing for Virtual Machine Power Savings

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Solution Overview

Problem

In hardware virtualization, the increased number of interrupts required for multiple virtual machines running on a single physical machine leads to more frequent processor interruptions, reducing opportunities for the processor to enter a low power mode, thus necessitating techniques to prolong idle periods while still providing timer ticks.

Innovation Solution

A method involving a virtual timer that receives requests for interrupts from guest operating systems, determines a system time for scheduling interrupts based on delay, and stores interrupt requests to coalesce interrupts, allowing the processor to enter a low power mode by delaying and grouping interrupt requests.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If periodic interrupts are generated for each virtual machine, then timer tick requirements are met, but processor interruption frequency increases and low power mode opportunities are reduced

Engineering Contradiction:
Improvetimer tick provisionVSAvoidprocessor power consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent combines multiple periodic interrupt requests from different virtual machines into a single consolidated interrupt handling event. The hypervisor merges interrupt requests that occur within a threshold time window, allowing the processor to service multiple virtual machines through a unified interrupt path rather than handling each request separately, thereby reducing overall interrupt frequency and enabling longer idle periods for power savings.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The system performs preliminary grouping of interrupt requests before actual interrupt handling occurs. By anticipating and consolidating interrupt requests in advance based on predicted timing patterns and threshold criteria, the system prepares merged interrupt events that reduce the total number of processor interruptions while ensuring timely delivery of timer ticks to all affected virtual machines.

Inventive Principle:
Principle #10Preliminary action

2Loss of energy

If interrupt requests are delayed and grouped, then processor can enter low power mode longer, but interrupt response time may increase

Engineering Contradiction:
Improvepower consumptionVSAvoidinterrupt response time
Core Design Contradiction:
Loss of energyVSLoss of time

Solution Approach 1:

The interrupt coalescing mechanism dynamically adjusts the threshold time window based on system conditions and virtual machine requirements. The system monitors interrupt patterns and modifies grouping parameters in real-time, allowing flexible balancing between power savings and response time. When response time sensitivity is high, the threshold is reduced; when power savings are prioritized, the threshold increases, creating a dynamic adaptation to varying operational demands.

Inventive Principle:
Principle #15Dynamics

3Productivity

If multiple virtual machines share interrupt handling, then interrupt frequency is reduced, but interrupt handling complexity increases

Engineering Contradiction:
Improveprocessor efficiencyVSAvoidinterrupt handling complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The hypervisor serves as an intermediary layer between virtual machines and the physical interrupt handling infrastructure. It implements a coalescing mechanism that receives interrupt requests from multiple virtual machines, consolidates them according to configured thresholds and timing criteria, and generates unified interrupt events. This intermediary approach abstracts the complexity from individual virtual machines while maintaining their timer tick requirements, centralizing the complexity management in the hypervisor layer.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10521265B2Coalescing periodic timer expiration in guest operating systems in a virtualized environment
Publication Date: 2019.12.31 MICROSOFT TECHNOLOGY LICENSING LLC
  • US10521265B2 patent drawing
  • US10521265B2 patent drawing
  • US10521265B2 patent drawing

AI summary

Techniques are disclosed for coalescing timer ticks generated by timers used to service guest operating systems executing in virtual machines. By coalescing timer ticks a logical processor can enter a low power mode thereby reducing power consumed by the system.