Virtual ToD Engine for Multiclock PTP Timing Anomaly Detection

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current techniques for routing PTP packets in a multiclock PTP architecture are resource intensive and lack security, making them prone to attacks such as man-in-the-middle attacks that can cause clock wander.

Innovation Solution

A virtual ToD engine is implemented on a network switch to facilitate timestamping and time error analysis, allowing for efficient management of ToD offsets and detection of timing anomalies, thereby enhancing resource efficiency and security.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple Master_toD circuits are implemented for each TimeTransmitter in a multiclock PTP architecture, then PTP communication between multiple TimeTransmitters and downstream TimeReceivers is enabled, but resource consumption increases significantly

Engineering Contradiction:
Improvesupport for multiple TimeTransmittersVSAvoidnumber of Master_toD circuits
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

A single virtualized Master_toD circuit performs the functions of multiple physical Master_toD circuits by dynamically allocating virtual instances based on demand. The virtualized circuit receives timestamps from a single physical source and generates virtual timestamps for multiple TimeTransmitters through software-based time offset calculations, eliminating the need for dedicated hardware circuits for each TimeTransmitter.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

Instead of copying physical Master_toD circuit hardware for each TimeTransmitter, the patent creates virtual copies of the Master_toD functionality through software simulation. These virtual instances replicate the timing functions using computational resources, allowing multiple TimeTransmitters to be supported without proportional increases in hardware complexity.

Inventive Principle:
Principle #26Copying

2Ease of manufacture

If PTP packets are transmitted without encryption in a multiclock PTP architecture, then protocol simplicity is maintained, but security against man-in-the-middle attacks is compromised

Engineering Contradiction:
Improveprotocol simplicityVSAvoidvulnerability to man-in-the-middle attacks
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The system continuously monitors TimeOfDay (ToD) offsets from multiple TimeTransmitters and compares them against expected values. When anomalies are detected—such as timestamps that deviate from the expected ToD pattern—the system generates alerts and can trigger corrective actions, providing feedback about potential security breaches without requiring encryption of the packet payloads.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent uses ToD offset values as an indicator or signature that changes under normal versus malicious conditions. By monitoring changes in the temporal characteristics (analogous to color changes) of timestamps, the system can detect when a TimeTransmitter is behaving anomalously, such as introducing deliberate timing deviations to cause clock wander or synchronization failures.

Inventive Principle:
Principle #32Color changes

Data Source

PatentUS20250150191A1Detecting and Handling Timing Anomalies Using Optimized Time of Days (ToDs) in a Multiclock Domain PTP Architecture
Publication Date: 2025.05.08 ALTERA CORP
  • US20250150191A1 patent drawing
  • US20250150191A1 patent drawing
  • US20250150191A1 patent drawing

AI summary

Integrated circuit devices, methods, and circuitry for a virtual time of day (ToD) engine to generate timestamps by using offsets associated with PTP clock domains. An integrated circuit device may include a number of ports configurable to communicate using timestamps corresponding to a number of Precision Time Protocol (PTP) clock domains. The integrated circuit device may also include a host data processing system to determine an offset for a first PTP clock domain of the plurality of PTP clock domains by calculating a difference between a first ToD provided by a clock source on the integrated circuit and one or more ToDs associated with the first PTP clock domain. The integrated circuit may further include a virtual ToD engine to generate a timestamp by adding the offset for the first PTP clock domain to a second ToD from the clock source and provide the timestamp to a port.