Virtual Time-of-Day Timing for PVT-Stable Line Card Sync
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Solution Overview
Problem
Network systems face challenges in maintaining precise time synchronization across line cards due to process, voltage, and temperature variations, leading to errors in time of day counters, which can result in packet loss and performance issues in real-time applications.
Innovation Solution
Implementing a virtual time of day approach using heartbeat clock signals with higher frequency than synchronization signals, time stamping these signals, and converting them to network time using a conversion factor to maintain accurate time of day values without physical counters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external ToD counters are used in each line card, then time synchronization can be maintained, but the system becomes vulnerable to PVT variations causing Continuous Time Error
Solution Approach 1:
The patent creates a virtual copy of the ToD counter function using software logic instead of physical hardware counters. The virtual ToD counter is implemented through a timing module that generates time values based on a reference clock, eliminating the need for external physical counters in each line card while maintaining synchronization accuracy and PVT stability.
2Use of energy by moving object
If SYNC signal frequency is kept low (1PPS), then power consumption is reduced, but timing resolution and synchronization precision deteriorate
Solution Approach 1:
The patent implements a multi-frequency periodic timing scheme where a high-frequency reference clock (e.g., 100 MHz) generates periodic timing signals, and a virtual ToD counter updates at lower frequencies (e.g., 1 PPS or 100 Hz) based on these periodic cycles. This allows the system to maintain high timing resolution through the high-frequency reference while consuming less power by updating the actual ToD value only periodically.
3Ease of operation
If physical ToD counters are implemented in each line card, then local time tracking is enabled, but device complexity and PVT sensitivity increase
Solution Approach 1:
The patent replaces the mechanical/physical ToD counter hardware with a software-based virtual counter implementation. The timing module uses a reference clock signal and software logic to generate virtual ToD values, eliminating the need for physical counter circuits in each line card while maintaining the ability to track local time and provide synchronization.
Data Source
AI summary
Time of day (ToD) registers provide respective virtual ToDs corresponding to the occurrence of edges of input clock signals being supplied to an integrated circuit. The integrated circuit generates a heartbeat clock signal having a frequency higher than a SYNC signal and time stamps the heartbeat clock signal to generate heartbeat time stamps. The heartbeat time stamps are used along with the time stamps of the input clock signals to determine the time of day corresponding to occurrences of edges of the input clock signals.