Virtual Topological Polygon Representation for EDA Data Processing

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Solution Overview

Problem

Conventional electronic design systems face inefficiencies in processing geometrical layout design data due to the lack of explicit storage of topological information, leading to increased computational time and memory requirements, especially when dealing with large datasets that exceed Random Access Memory (RAM) capacity.

Innovation Solution

The method involves extracting topological characteristics data to form virtual topological polygons, represented by Scan Orders (SO), determining dimensional data to form sized polygons, and instantiating these polygons with spatial data, allowing for efficient storage and processing by aggregating similar topological characteristics and reducing memory needs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional systems store geometrical layout design data without explicit topological information, then storage simplicity is maintained, but computational time and memory requirements increase significantly

Engineering Contradiction:
Improvecomputational speedVSAvoiddata structure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments geometrical layout data into distinct components: topological characteristics data (describing shape and connectivity) and dimensional/spatial data. This segmentation allows topological information to be extracted and stored separately, enabling efficient reuse across multiple operations without reprocessing the entire dataset, thus resolving the contradiction between computational speed and data structure complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary extraction and storage of topological characteristics data before actual processing operations. By pre-computing and storing topological features (such as connectivity relationships, shape descriptors) in an accessible format, the system avoids repeated computationally intensive calculations during subsequent operations, thereby improving productivity while maintaining manageable data structure complexity through organized storage.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If each polygon is analyzed separately for topological information, then processing accuracy is maintained, but additional RAM resources are demanded

Engineering Contradiction:
Improvetopological analysis accuracyVSAvoidmemory capacity
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent merges topological characteristics extraction across multiple polygons by identifying and storing common topological patterns and relationships in a shared data structure. Instead of maintaining separate complete representations for each polygon, the system combines redundant topological information, allowing accurate analysis while reducing the total quantity of data stored in memory.

Inventive Principle:
Principle #5Merging (Combining)

3Quantity of substance

If virtual memory systems are used to store polygonal data on hard disk, then storage capacity is increased, but data fetching speed decreases significantly

Engineering Contradiction:
Improvestorage capacityVSAvoiddata access speed
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The patent extracts only the essential topological characteristics data from the complete geometrical layout and stores this condensed representation in accessible memory formats. By taking out only the critical topological features rather than storing entire polygon datasets, the system achieves sufficient storage capacity for analysis while maintaining fast data access speeds, avoiding the need to frequently fetch large datasets from virtual memory on hard disk.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS8136058B2Method and system for representing geometrical layout design data in electronic design systems
Publication Date: 2012.03.13 SIEMENS INDUSTRY SOFTWARE INC
  • US8136058B2 patent drawing
  • US8136058B2 patent drawing
  • US8136058B2 patent drawing

AI summary

A method and system of representing geometrical layout design data having a plurality of polygons in electronic design systems is provided. The method includes extracting topological characteristics data corresponding to one or more polygons to form one or more virtual topological polygon. Each virtual polygon is represented by Scan order (SO), with SO corresponding to order in which the vertices of polygon are encountered by a sweep line moving in predefined direction with a predefined angular orientation. The method further includes determining dimensional data corresponding to each polygon to form one or more sized polygons using one or more virtual topological polygon. Thereafter, the spatial data corresponding to each sized polygon is extracted to instantiate each sized polygon.