Virtual Transparent Clock for VM Timing Synchronization
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Solution Overview
Problem
Virtual machine (VM) host systems face significant timing inaccuracies due to variable clock speeds and unknown delays in virtual switches, which hinder precise timing synchronization essential for time-sensitive applications.
Innovation Solution
Implementing a virtual transparent clock within the virtualization layer to determine intra-switch delay times for timing packets, allowing for accurate correction and synchronization of VM guest platforms' clocks using Precision Time Protocol (PTP) messages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If virtual machine host systems use standard timing protocols without correction, then device complexity is reduced, but timing precision deteriorates due to variable delays in virtual switches
Solution Approach 1:
The patent introduces a virtual transparent clock as an intermediary component within the virtual switch. This mediator measures the actual residence time of PTP packets traversing the virtual switch and communicates this delay information to endpoint devices, enabling them to correct timing calculations without requiring complex changes to the overall system architecture
Solution Approach 2:
The patent replaces the need for complex hardware timing mechanisms in virtualized environments with a software-based transparent clock implementation. Instead of relying on precise hardware clock synchronization through the virtualization layer, the system uses software to measure and communicate delay values, substituting mechanical/hardware timing with a software correction mechanism
2Measurement precision
If virtual transparent clocks are implemented to measure intra-switch delay, then timing precision is improved, but device complexity increases due to additional measurement and communication mechanisms
Solution Approach 1:
The virtual transparent clock is designed to perform multiple functions: it measures packet residence time, communicates delay information to endpoint devices, and operates transparently with existing PTP protocols. This multi-functionality reduces the need for separate dedicated components for each function, thereby limiting the increase in overall system complexity
3Measurement precision
If PTP packets are used for synchronization without delay correction, then ease of operation is maintained, but timing accuracy deteriorates due to unaccounted virtual switch delays
Solution Approach 1:
The virtual transparent clock automatically measures the residence time of PTP packets and generates correction information without requiring manual configuration or intervention. The system self-services by capturing timing data, calculating delays, and communicating correction values, thereby maintaining ease of operation while improving accuracy
Data Source
AI summary
Network timing synchronization for virtual machine (VM) host systems and related methods are disclosed that provide synchronization of master/slave clocks within VM host hardware systems. Master timing messages are sent from the master clocks to slave clocks within VM guest platforms hosted by the VM host hardware system within a virtualization layer, and return slave timing messages are communicated from the VM guest platforms to the master clock. Virtual switches within the virtualization layer use virtual transparent clocks to determine intra-switch delay times for the timing packets traversing the virtual switch. These intra-switch delay times are then communicated to target destinations and used to account for variations in packet transit times through the virtual switch. The VM guest platforms synchronize their timing using the timing messages. The master/slave timing messages can be PTP (Precision Time Protocol) timing messages and/or timing messages based upon some other timing protocol.