Virtual Vector Processing via Dynamic Core Allocation

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Solution Overview

Problem

Existing vector processors are limited by fixed vector sizes and are often cost-prohibitive, restricting their use to specific applications and lacking flexibility in handling variable vector lengths.

Innovation Solution

The implementation of virtual vector processing in computing systems, where processor cores can dynamically allocate and manage vector operations across multiple cores, allowing for variable vector lengths and efficient resource utilization without a dedicated vector unit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a dedicated vector processor is used, then processing performance is improved, but system cost increases

Engineering Contradiction:
Improveprocessing performanceVSAvoidsystem cost
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The patent combines vector processing capabilities with general-purpose processor cores by implementing vector instructions within the existing core architecture. This merging eliminates the need for separate dedicated vector processor units, thereby maintaining high processing performance while reducing system cost and complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The processor core is designed to handle both scalar and vector operations using the same hardware resources. The vector processing unit (VPU) is integrated into the general-purpose core, allowing it to perform multiple functions including scalar arithmetic, vector arithmetic, and control operations, thus eliminating the need for dedicated vector hardware.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If the vector processor is designed for a specific vector size, then processing efficiency is improved, but adaptability to different applications deteriorates

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidadaptability to different applications
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The vector processing unit is designed with dynamic vector length capability, allowing the vector size to be adjusted based on the specific application requirements. The VPU can process vectors of varying lengths by dynamically configuring the number of elements processed in each operation, thus maintaining high processing efficiency across different applications without being locked into a fixed vector size.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements variable vector length processing by changing the parameter of vector size dynamically. The VPU allows the vector length to be modified through software control or instruction parameters, enabling the same hardware to efficiently process different vector sizes (e.g., 4, 8, 16, 32 elements) depending on the application needs, thereby achieving both efficiency and adaptability.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If processing operations are distributed across multiple cores, then resource utilization is improved, but coordination complexity increases

Engineering Contradiction:
Improveresource utilizationVSAvoidcoordination complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent divides vector processing operations into segments that can be distributed across multiple processor cores. Each core can independently handle a portion of the vector data, and the results are aggregated at the end. This segmentation improves resource utilization by parallelizing operations across cores while managing coordination complexity through structured data flow and result collection mechanisms.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10768989B2Virtual vector processing
Publication Date: 2020.09.08 INTEL CORP
  • US10768989B2 patent drawing
  • US10768989B2 patent drawing
  • US10768989B2 patent drawing

AI summary

Methods and apparatus to provide virtualized vector processing are described. In one embodiment, one or more operations corresponding to a virtual vector request are distributed to one or more processor cores for execution.