Virtual Verification Machine for Offline IC Design Debugging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The complexity of integrated circuit (IC) design requires substantial resources for validation, emulation, and debugging, leading to limited access to shared hardware-based verification platforms, which severely affects design schedules due to their high cost and shared usage.
Innovation Solution
A system and method that records essential information during IC design operations, allowing for offline debugging using a virtual verification machine (VVM) to replay and analyze design tests, enabling detailed analysis without relying on shared hardware-based verification platforms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardware-based verification platforms are used for validation, emulation, and debugging, then verification capability and analysis power are improved, but resource availability and access efficiency deteriorate due to limited shared resources and high cost
Solution Approach 1:
The patent creates a virtual verification machine that copies the essential functionality of the hardware-based verification platform. The VVM captures and stores verification data during hardware emulation, then replays this data offline to replicate the verification and debugging capabilities without requiring continuous access to the expensive shared hardware platform, thereby improving resource availability while maintaining verification capability
Solution Approach 2:
The system performs preliminary data capture and storage during the hardware emulation phase. Essential verification data, signals, and states are recorded and stored in a database before the actual verification analysis is needed. This preliminary action allows subsequent offline replay and analysis without requiring the hardware platform to be available, resolving the contradiction between verification capability and resource availability
2Reliability
If shared hardware-based verification platforms are used, then comprehensive verification analysis is achieved, but design schedule efficiency deteriorates due to limited access and queuing delays
Solution Approach 1:
By creating a virtual verification machine that copies hardware verification functionality, designers can perform comprehensive verification analysis offline without queuing for shared hardware platform access. The VVM replays captured verification data to achieve the same verification completeness as the hardware platform while eliminating wait time and schedule delays
Solution Approach 2:
The system enables continuous verification activities by allowing offline replay and analysis whenever needed, without being constrained by hardware platform availability or scheduling. Designers can continuously work on verification and debugging tasks using the VVM, eliminating idle time and maintaining productive workflow, thus improving design schedule efficiency while maintaining verification completeness
3Productivity
If offline debugging with virtual verification machine is implemented, then resource dependency is reduced, but verification fidelity may deteriorate without real hardware
Solution Approach 1:
The virtual verification machine creates accurate copies of hardware verification data, including signal values, timing information, and system states. By faithfully reproducing the hardware platform's verification data in software, the VVM maintains verification fidelity while enabling resource independence, as the copied data preserves all necessary verification information without requiring actual hardware
Solution Approach 2:
The system introduces a data capture and replay mechanism as an intermediary between the hardware platform and the verification analysis process. This intermediary layer captures essential verification data from the hardware and replays it in the virtual environment, preserving verification fidelity while allowing offline analysis. The intermediary ensures that the VVM receives accurate representations of hardware behavior, maintaining reliability despite physical separation from the actual hardware
Data Source
AI summary
Essential information for system operations, memory analysis, and design signal analysis is captured while a hardware based verification platform is performing emulation and testing. This recorded information is then accessible via a memory device and can be used to perform offline debugging with a virtual verification machine (VVM). Users can then release the shared resources and run operation commands to control replay of the design test or emulation in offline mode. Users can access any point in time of the recorded emulation in order to perform detailed design analysis and debugging operations. Offline analysis and debugging may include running certain design cycles, rerunning the emulation until the design reaches a certain state, evaluating memory contents in the design, evaluating design signals for any node in the design, etc.