Virtual Wafer FDC Modeling for Multi-Chamber Semiconductor Processes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The high investment costs and long time required to improve semiconductor processes through experiments on actual wafers when training semiconductor process models using process parameter values.
Innovation Solution
A semiconductor production system and method that utilizes virtual wafers to train fault detection and classification machine learning models, allowing for the generation of predicted FDC values and improved semiconductor yields by adjusting setting values in chambers, thereby reducing the need for extensive experimentation on actual wafers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If actual wafers are used for training semiconductor process models, then model accuracy is improved, but investment costs and time consumption increase significantly
Solution Approach 1:
The patent creates virtual wafers that replicate the essential characteristics and process parameters of actual wafers. These virtual copies are used for training machine learning models, allowing accurate process modeling without the need to physically process numerous actual wafers, thereby reducing time consumption while maintaining model accuracy.
Solution Approach 2:
The patent introduces virtual wafers as an intermediary between the physical wafer processing system and the machine learning training process. This intermediary layer allows the system to gather training data through virtual simulations rather than direct physical experimentation, significantly reducing the time and resources required while preserving the accuracy needed for process optimization.
2Measurement precision
If actual wafers are used for training semiconductor process models, then model accuracy is improved, but investment costs increase significantly
Solution Approach 1:
The patent creates virtual wafers that replicate the essential characteristics and process parameters of actual wafers. These virtual copies are used for training machine learning models, allowing accurate process modeling without the need to physically process numerous actual wafers, thereby reducing time consumption while maintaining model accuracy.
Solution Approach 2:
The patent employs virtual wafers that can be generated, used, and discarded computationally without any physical resource consumption. These virtual objects serve as disposable training data sources that eliminate the high costs associated with actual wafer fabrication, testing, and analysis while providing sufficient data for accurate model training.
3Loss of time
If virtual wafers are used for training FDC models, then time and cost are reduced, but model training complexity increases
Solution Approach 1:
The patent segments the wafer processing system into virtual representations that can be independently generated and manipulated. By dividing the complex physical system into discrete virtual wafer objects with specific parameters, the system simplifies the training process while reducing development time, as each virtual wafer can be processed and analyzed separately through automated computational methods.
Data Source
AI summary
A semiconductor production system includes: a first chamber that is configured to be set to a first setting value and process wafers; a second chamber that is configured to be set to a second setting value and process the wafers processed in the first chamber; and a fault detection and classification (FDC) modeling module configured to: train a first FDC machine learning model to generate, based on the first setting value and first FDC values sensed with respect to the wafers processed in the first chamber, first predicted FDC values with respect to first virtual wafers in the first chamber; and train a second FDC machine learning model to generate, based on the second setting value and second FDC values sensed with respect to the wafers processed in the second chamber, second predicted FDC values with respect to second virtual wafers in the second chamber.