Virtualizing Micro-Op Cache via Conventional Storage
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Solution Overview
Problem
Modern CPU cores face inefficiencies due to the limited size of the micro-operation cache, leading to frequent evictions and re-decoding of instructions, which increases power consumption and reduces energy efficiency.
Innovation Solution
Implementing a virtualization method where evicted micro-operations are written to a conventional cache subsystem, allowing subsequent executions to retrieve them instead of refetching and re-decoding, and using a pre-decode cache to store metadata for efficient lookup and bypassing the decode unit when possible.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the micro-operation cache size is increased to reduce instruction re-decoding, then the hit rate is improved, but the CPU core floorplan is disrupted
Solution Approach 1:
The patent implements a hierarchical cache structure where a small dedicated micro-operation cache is nested within or alongside the conventional cache subsystem. Evicted micro-operations are stored in the conventional cache, creating a nested arrangement that provides extended caching capacity without disrupting the core floorplan. This nested structure allows the system to achieve higher effective hit rates while maintaining the original CPU core layout.
2Use of energy by moving object
If the micro-operation cache size is increased to reduce instruction re-decoding, then power consumption is reduced, but the CPU core floorplan is disrupted
Solution Approach 1:
By nesting the micro-operation cache functionality within the existing conventional cache infrastructure, the patent avoids the need for a larger dedicated cache that would disrupt the floorplan. The conventional cache serves dual purposes: storing both instructions and evicted micro-operations, thereby reducing power consumption without requiring additional space that would alter the CPU core layout.
Solution Approach 2:
The conventional cache subsystem is designed to perform multiple functions: storing instructions, storing evicted micro-operations, and providing virtualized micro-operation cache functionality. This multi-functional approach allows the system to reduce power consumption through extended micro-operation caching while using existing hardware resources, avoiding floorplan disruption.
3Productivity
If instructions are frequently re-decoded due to micro-operation cache evictions, then energy efficiency is reduced, but the decode unit usage increases
Solution Approach 1:
Instead of discarding evicted micro-operations, the patent recovers them by storing in the conventional cache subsystem. When these micro-operations are needed again, they are retrieved from the conventional cache rather than being re-decoded from instructions. This recovery mechanism eliminates redundant decoding operations, improving energy efficiency and reducing decode unit power consumption.
Solution Approach 2:
The conventional cache subsystem acts as an intermediary between the micro-operation cache and the decode unit. When micro-operations are evicted from the micro-operation cache, the intermediary conventional cache stores them, preventing the need for immediate re-decoding. This intermediary structure reduces the frequency of decode unit activation, thereby reducing its power consumption and improving overall energy efficiency.
Data Source
AI summary
Systems, apparatuses, and methods for virtualizing a micro-operation cache are disclosed. A processor includes at least a micro-operation cache, a conventional cache subsystem, a decode unit, and control logic. The decode unit decodes instructions into micro-operations which are then stored in the micro-operation cache. The micro-operation cache has limited capacity for storing micro-operations. When new micro-operations are decoded from pending instructions, existing micro-operations are evicted from the micro-operation cache to make room for the new micro-operations. Rather than being discarded, micro-operations evicted from the micro-operation cache are stored in the conventional cache subsystem. This prevents the original instruction from having to be decoded again on subsequent executions. When the control logic determines that micro-operations for one or more fetched instructions are stored in either the micro-operation cache or the conventional cache subsystem, the control logic causes the decode unit to transition to a reduced-power state.