Virtualized Control Threads in Multi-Core Processors
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Solution Overview
Problem
Symmetric multi-core processors (MCPs) suffer from low utilization and power wastage due to design inflexibility, leading to continuous leakage current in stand-by sub-processing elements, resulting in inefficient power usage and challenging optimization as processor dimensions increase.
Innovation Solution
The implementation of virtualized control threads within main processing elements to manage and control groups of sub-processing elements, allowing for dynamic power management and optimized resource allocation by assigning virtualized control threads to specific groups of sub-processing elements, enabling efficient power usage and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If stand-by sub-processing elements are maintained in a symmetric MCP, then design inflexibility is avoided, but continuous leakage current causes power wastage
Solution Approach 1:
The patent implements dynamic power management by allowing sub-processing elements to transition between active and stand-by states based on workload demands. The main processing element can dynamically allocate and de-allocate sub-processing elements, enabling the system to adapt its power consumption profile to actual computational needs rather than maintaining a fixed symmetric configuration.
Solution Approach 2:
The main processing element serves multiple functions: it acts as a full processing element when needed and simultaneously functions as a controller for sub-processing elements. This multi-functionality allows the system to optimize power usage by having the MPE manage both computation and resource allocation, eliminating the need for dedicated control hardware while reducing overall power consumption.
2Productivity
If a larger number of sub-processing elements are utilized, then processing capacity increases, but MCP utilization becomes difficult to optimize
Solution Approach 1:
The patent introduces virtualization threads as intermediary software layers that manage the allocation and control of sub-processing elements. These virtualization threads act as mediators between the main processing element and multiple sub-processing elements, simplifying the control architecture by providing a standardized interface for resource management regardless of the number of SPEs involved.
Solution Approach 2:
The patent segments the processing elements into one main processing element and multiple sub-processing elements with different functional capabilities. This segmentation allows the system to scale processing capacity by adding specialized SPEs while keeping the control logic centralized in the MPE, thereby managing complexity through functional differentiation rather than uniform replication.
3Speed
If stand-by sub-processing elements are maintained, then rapid activation is possible, but high levels of power are consumed continuously
Solution Approach 1:
The patent implements periodic power management where sub-processing elements are activated only when needed based on workload demands. Instead of maintaining continuous stand-by power, the system periodically evaluates the need for additional processing capacity and activates or deactivates SPEs accordingly, creating a rhythm of power consumption that matches actual computational requirements.
Data Source
AI summary
This invention describes an apparatus, computer architecture, method, operating system, compiler, and application program products for MPEs as well as virtualization in a symmetric MCP. The disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs. The apparatus enables virtualized control threads within MPEs to be assigned to different groups of SPEs for controlling the same. The apparatus further includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements.