Virtualized ECC Controller for NAND Memory Power and Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing communication devices face challenges with error detection and correction in NAND memory due to technology-specific ECC algorithms, which are costly to update and restrict compatibility with different memory technologies, leading to inefficiencies and increased power consumption.
Innovation Solution
A virtualized ECC NAND controller is introduced to manage multiple NAND memory structures, executing the ECC algorithm externally and providing a unified interface, allowing the host CPU to treat multiple NAND devices as a single memory system, thereby reducing power consumption and enabling flexibility across different memory technologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If technology-specific ECC algorithms are implemented in NAND memory devices, then error correction capability is improved, but device complexity and cost to update increase
Solution Approach 1:
The ECC algorithm execution is extracted from the NAND memory device and moved to an external host processor. The patent implements a virtualized ECC controller that runs ECC algorithms externally, allowing the NAND device to be technology-agnostic while maintaining error correction capabilities. This extraction resolves the contradiction by improving reliability through centralized ECC management while reducing device complexity and update costs at the memory device level.
Solution Approach 2:
The patent creates a universal interface layer that allows a single host platform to manage multiple NAND memory technologies through a standardized virtualized controller. This multi-functional approach enables the same ECC infrastructure to serve different NAND technologies (SLC, MLC, TLC, QLC) without requiring technology-specific hardware modifications, thus improving reliability across diverse technologies while controlling device complexity.
2Productivity
If multiple NAND memory structures are managed separately, then individual device performance is optimized, but system power consumption increases
Solution Approach 1:
The patent merges multiple NAND memory structures into a unified virtualized memory system managed by a single ECC controller. By combining separate memory devices into a single addressable namespace and consolidating ECC operations, the system achieves better power efficiency while maintaining productivity. The unified management allows for coordinated operations that reduce redundant processing and lower overall power consumption compared to separate management of each device.
3Adaptability or versatility
If host platform is modified to support new NAND technologies, then compatibility is improved, but system complexity and cost increase
Solution Approach 1:
The patent introduces a virtualized ECC controller as an intermediary layer between the host platform and multiple NAND memory technologies. This mediator handles technology-specific variations and presents a unified interface to the host, allowing compatibility with different NAND technologies without modifying the host platform itself. The intermediary absorbs the complexity of supporting multiple technologies while keeping the host platform simple and cost-effective.
4Reliability
If ECC algorithms are executed internally in each NAND device, then data reliability is improved, but manufacturing cost and update cost increase
Solution Approach 1:
The patent extracts ECC algorithm execution from individual NAND memory devices and relocates it to an external host-based virtualized controller. This extraction maintains data reliability through centralized error correction while significantly reducing manufacturing costs by eliminating the need for complex ECC hardware in each memory device. Updates to ECC algorithms can be performed through software changes on the host platform rather than requiring hardware modifications or device recalls.
Data Source
AI summary
Various embodiments disclose a controller to manage memory devices. In an exemplary method, signals are exchanged with a host processor to allow the host processor to communicate with multiple memory devices in a memory stack as a single device, regardless of an actual number of memory devices within the memory stack. Power is provided to a single one of the multiple memory devices in the memory stack at a time to reduce power consumption. Other methods, apparatuses, and devices are also disclosed.