Virtualized ECC NAND Controller for Multi-Technology Flash Memory
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Solution Overview
Problem
Existing ECC algorithms in NAND memory devices are technology-specific, costly to update, and restrict flexibility when switching between different memory technologies or configurations, such as from Single Level Cell (SLC) to Multi Level Cell (MLC), and require modifications for changes in die area and command sets.
Innovation Solution
A virtualized ECC NAND controller is introduced to manage multiple NAND memory structures, executing the ECC algorithm externally and providing a unified interface, allowing the host CPU to treat multiple NAND devices as a single memory system, reducing power consumption and enabling adaptation to different technologies and configurations without modifying the host platform.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If technology-specific ECC algorithms are implemented within each NAND memory device, then error correction capability is provided, but compatibility with different memory technologies is restricted and updates are costly
Solution Approach 1:
The ECC algorithm functionality is extracted from the individual NAND memory devices and relocated to an external host processor or controller. This allows the ECC engine to operate independently of the specific NAND technology, enabling support for multiple memory types (SLC, MLC, TLC, QLC) without requiring technology-specific implementations within each memory device.
Solution Approach 2:
The external virtualized ECC controller is designed to provide universal error correction capabilities across different NAND memory technologies. By implementing a single standardized ECC interface at the host level, the system can adapt to various memory types and future technologies without requiring separate ECC implementations for each device.
2Reliability
If multiple NAND memory structures are managed with separate ECC implementations, then each device can operate independently, but power consumption increases and system complexity grows
Solution Approach 1:
Multiple ECC operations across different NAND memory devices are merged into a single virtualized ECC controller instance running on the host processor. This consolidation eliminates redundant ECC engine implementations in each memory device, reducing overall power consumption while maintaining error correction capabilities across all memory structures.
Solution Approach 2:
The host processor acts as an intermediary that manages ECC operations for multiple NAND devices centrally. Instead of each memory device having its own dedicated ECC logic, the host processor mediates all ECC functions, optimizing resource utilization and reducing power consumption through shared computational resources.
3Adaptability or versatility
If fixed host platforms are updated to support new NAND technologies, then compatibility is improved, but cost and complexity of updates increase
Solution Approach 1:
The ECC controller is implemented as a virtualized software component or flexible firmware module on the host processor rather than a fixed hardware implementation. This dynamic approach allows the ECC algorithm and parameters to be updated via software to support new NAND technologies (such as QLC or PLC) without requiring costly hardware platform updates or changes to the physical host platform architecture.
Data Source
AI summary
A single virtualized ECC NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller allows the host processor to drive the stack of flash memory devices as a single NAND chip while the controller redirects the data to the selected NAND memory device in the stack.