Virtualized Domain-Specific Hardware Accelerator With Isolated IPC
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Solution Overview
Problem
Embedded computing systems are vulnerable to security threats and system failures, particularly in safety-critical applications like advanced driver assistance systems, due to the lack of effective isolation and verification of message requests between hardware accelerators.
Innovation Solution
A trusted and sandboxed communication interface is implemented between HWA thread users and domain specific HWAs, managed by a multi-HWA function controller, which filters and schedules message requests, performs intelligent scheduling based on HWA capabilities, and provides privileged credential verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a hardware accelerator is added to improve computational performance, then processing speed increases, but security vulnerabilities increase due to lack of isolation mechanisms
Solution Approach 1:
The communication interface is segmented into multiple isolated channels, each dedicated to specific HWA thread users. This segmentation prevents unauthorized access and cross-contamination between different users, allowing multiple hardware accelerators to operate at high speed while maintaining security through physical and logical isolation of communication paths.
Solution Approach 2:
A trusted communication interface acts as an intermediary between HWA thread users and domain-specific hardware accelerators. This intermediary verifies credentials, filters message requests, and manages communication protocols, enabling fast direct communication while maintaining security through centralized verification and control mechanisms.
2Adaptability or versatility
If communication interfaces are opened for multiple HWA thread users, then system versatility improves, but security risks increase due to potential malicious intrusions
Solution Approach 1:
The communication interface is divided into multiple isolated communication channels, each serving specific HWA thread users. This segmentation allows the system to support multiple users and applications (versatility) while preventing malicious intrusions from affecting other users through the isolation barriers built into each channel's credential verification mechanism.
Solution Approach 2:
Credential verification is performed preliminarily at the communication interface before messages are routed to hardware accelerators. By verifying credentials and establishing trusted communication paths in advance, the system can safely accommodate multiple users and applications without exposing internal components to potential security threats.
3Reliability
If credential verification is implemented for all message requests, then security improves, but processing time increases
Solution Approach 1:
Credential verification is performed preliminarily when communication channels are established and registered, rather than for every individual message. This preliminary verification creates trusted communication paths that allow subsequent messages to be processed quickly without repeated verification overhead, maintaining both security and processing speed.
Solution Approach 2:
Each communication channel is configured with its own credential verification mechanisms and security parameters during setup. Once established, the channels autonomously enforce their security rules without requiring continuous external verification, reducing processing time while maintaining security through self-enforcing trusted pathways.
Data Source
AI summary
This disclosure relates to various implementations an embedded computing system. The embedded computing system comprises a hardware accelerator (HWA) thread user and a second HWA thread user that creates and sends out message requests. The HWA thread user and the second HWA thread user is communication with a microcontroller (MCU) subsystem. The embedded computing system also comprises a first inter-processor communication (IPC) interface between the HWA thread user and the MCU subsystem and a second IPC interface between the second HWA thread user and the MCU subsystem, where the first IPC interface is isolated from the second IPC interface. The MCU subsystem is also in communication with a first domain specific HWA and a second domain specific HWA.