Virtualized I/O Device Sharing in Distributed Processing Nodes

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Solution Overview

Problem

Current computing systems face performance issues when sharing Input/Output (I/O) devices across multiple processing nodes due to inefficient routing of high bandwidth traffic and interrupt notifications, as existing bus standards like PCI Express do not allow direct communication between I/O devices and processing units.

Innovation Solution

Implementing a distributed processing node system with a switched fabric hierarchy that allows direct access to a shared I/O device by multiple endpoint nodes, using modified address translation units and dedicated hardware for interrupt handling, and establishing a software communications agent for low-bandwidth messaging and exception handling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a single I/O device is shared among multiple processing nodes using traditional PCI Express bus standards, then device sharing capability is improved, but communication bandwidth and interrupt handling performance deteriorate due to indirect routing through the root complex

Engineering Contradiction:
ImproveI/O device sharing capabilityVSAvoidcommunication bandwidth and interrupt handling performance
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent segments the I/O device into multiple virtual functions (VFs), with each VF assigned to a specific processing node. This segmentation allows direct communication between each processing node and its assigned virtual function, eliminating the need for all communications to route through the root complex. The segmentation of the I/O device into isolated communication paths resolves the contradiction by enabling both device sharing and high-performance direct communication.

Inventive Principle:
Principle #1Segmentation

2Productivity

If direct communication paths are established between processing nodes and I/O devices, then communication bandwidth and latency are improved, but system complexity increases due to modified address translation units and dedicated hardware

Engineering Contradiction:
Improvecommunication bandwidth and latencyVSAvoidaddress translation units and hardware structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary software communications agent that manages the complexity of direct communication paths. This agent handles address translation and coordination between processing nodes and the shared I/O device, allowing the hardware to maintain relatively simple structures while achieving high-performance direct communication. The intermediary software layer absorbs much of the complexity, resolving the contradiction between direct communication performance and hardware complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Speed

If interrupt logic is distributed to individual processing nodes for handling interrupts from assigned virtual functions, then interrupt handling speed is improved, but system complexity increases due to distributed interrupt management

Engineering Contradiction:
Improveinterrupt handling speedVSAvoidinterrupt management system
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent applies local quality by assigning specific interrupt handling capabilities to specific processing nodes based on their assigned virtual functions. Each processing node has dedicated interrupt logic for its assigned VFs, enabling fast local interrupt handling. The root complex retains interrupt handling for other functions, creating a distributed but organized interrupt management system. This local specialization resolves the contradiction by enabling fast interrupt handling at each node while maintaining overall system coordination.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10067900B2Virtualized I/O device sharing within a distributed processing node system
Publication Date: 2018.09.04 ORACLE INT CORP
  • US10067900B2 patent drawing
  • US10067900B2 patent drawing
  • US10067900B2 patent drawing

AI summary

A system that includes a switched fabric hierarchy (e.g., a PCIe hierarchy) may realize efficient utilization of a shared I/O device (e.g., a network or storage switch) across multiple physically separate processing nodes (endpoints). For example, each processing node (endpoint) in a distributed processing system may be allocated a portion of the address map of a shared I/O device and may host a device driver for one of multiple virtual functions implemented on the shared device. Following enumeration and initialization of the hierarchy by the root complex, the endpoints may access the virtual functions directly (without intervention by the root complex). Data and interrupt traffic between endpoints and virtual functions may take place over peer-to-peer connections. Interrupt reception logic in each endpoint may receive and handle interrupts generated by the virtual functions. The root complex may host a device driver for a physical function on the shared device.