Virtualized L1 Cache Layout for VIPT Synonym Disambiguation
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Solution Overview
Problem
The use of virtually indexed physically tagged (VIPT) caches in microprocessors can lead to synonym issues due to the same physical cache block appearing at two different virtual indexes, which limits cache size and increases tag array depth, complicating pipeline operations.
Innovation Solution
The L1 cache is split into multiple logical caches sharing the same physical implementation, with an outer memory system resolving ownership conflicts and disambiguating synonyms using a coherence protocol, allowing larger cache sizes and simpler pipeline management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a VIPT cache is used to enable virtual addressing, then cache access can be overlapped with physical address translation, but synonym issues arise where the same physical cache block appears at different virtual indexes
Solution Approach 1:
The L1 cache is divided into multiple logical caches (e.g., L1-0, L1-1, L1-2, L1-3) that share the same physical implementation. Each logical cache handles a specific portion of the virtual address space, eliminating synonym conflicts by ensuring that each physical block maps to a unique logical cache. This segmentation allows the cache to maintain larger sizes without increasing tag array depth, as each logical cache has its own independent tagging structure.
2Quantity of substance
If the L1 cache size is increased beyond virtual memory page size, then more cache capacity is available, but the number of ways and tag array depth must be increased
Solution Approach 1:
The patent introduces a new dimension of organization by creating multiple logical caches that share physical resources. Instead of increasing tag array depth within a single cache structure, the solution adds a logical cache dimension where each logical cache manages a portion of the virtual address space. This allows the total cache capacity to exceed page size limits while keeping individual tag arrays manageable in depth.
3Productivity
If multiple logical caches share the same physical implementation, then larger cache sizes are enabled with simpler pipeline management, but coherence protocol complexity increases
Solution Approach 1:
The outer memory system is designed to universally handle coherence for multiple logical caches through a single coherence protocol interface. The same coherence mechanisms (e.g., snoop filters, directory-based protocols) that manage coherence between separate physical caches are applied to manage coherence between the logical caches. This allows the system to benefit from multiple logical caches for pipeline efficiency while avoiding the need for separate coherence protocols for each logical cache.
Data Source
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AI summary
Systems and methods are disclosed for virtualized caches. For example, an integrated circuit (e.g., a processor) for executing instructions includes a virtually indexed physically tagged first-level (L1) cache configured to output to an outer memory system one or more bits of a virtual index of a cache access as one or more bits of a requestor identifier. For example, the Ll cache may be configured to operate as multiple logical Ll caches with a cache way of a size less than or equal to a virtual memory page size. For example, the integrated circuit may include an L2 cache of the outer memory system that is configured to receive the requestor identifier and implement a cache coherency protocol to disambiguate an Ll synonym occurring in multiple portions of the virtually indexed physically tagged Ll cache associated with different requestor identifier values.