Virtualized Multicore Systems With Extended ISA Heterogeneity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Multicore processors become highly specialized when using application-specific accelerators or custom cores, reducing market availability and increasing development costs due to application-specific designs, which complicates load balancing and power management in heterogeneous systems.
Innovation Solution
Implementing a virtualization architecture with extensions to a common instruction set architecture (ISA) for data plane processor cores, allowing for load balancing and power optimization by migrating tasks between cores with equivalent instruction sets and using software equivalents for specialized processing elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If application-specific accelerators or custom processor cores are used to specialize data plane processing, then processing efficiency for specific applications is improved, but device complexity and development costs increase
Solution Approach 1:
The patent implements a universal base instruction set architecture that can be extended with optional specialized units. Different processor cores can share the same base ISA while having different combinations of optional specialized units (such as cryptography accelerators, multimedia engines, or network processing units). This allows a single processor design to serve multiple applications and markets, reducing development costs while maintaining high processing efficiency for specific workloads.
2Productivity
If processor cores are highly specialized for specific applications, then performance for those applications is improved, but adaptability to other applications is reduced
Solution Approach 1:
The patent enables dynamic configuration where processor cores can be selectively activated or deactivated based on application requirements. The system can dynamically allocate specialized processing resources to match the current workload, allowing the same hardware platform to adapt to different applications over time. This dynamic approach maintains high performance for specialized tasks while preserving versatility across different application domains.
3Productivity
If heterogeneous processor cores with different instruction sets are used, then specialized processing capability is improved, but load balancing and task migration become more difficult
Solution Approach 1:
The patent enforces homogeneity by requiring all processor cores to implement a common base instruction set architecture. This base ISA serves as a standardized interface that simplifies task migration and load balancing, as code can be executed on any core in the system. Specialized functionality is added through optional extensions that build upon this common foundation, allowing heterogeneous capabilities to coexist with homogeneous control mechanisms.
Data Source
AI summary
A system on a chip may include a plurality of data plane processor cores sharing a common instruction set architecture. At least one of the data plane processor cores is specialized to perform a particular function via extensions to the otherwise common instruction set architecture. Such systems on a chip may have reduced physical complexity, cost, and time-to-market, and may provide improvements in core utilization and reductions in system power consumption.