Virtualized Processor Co-Simulation for SoC Firmware Verification
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Solution Overview
Problem
Simulating large circuits, especially those including central processing units (CPUs), can be time-consuming and produce overwhelming amounts of data, making it difficult to gain insights into errors.
Innovation Solution
The use of system virtualization based co-simulation, where a virtualized processor executes certain firmware instructions and peripheral firmware instructions are sent over a network connection for simulation by hardware description language (HDL) code, reducing the burden on HDL simulators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If hardware description language code is used to simulate large circuits with CPUs, then simulation accuracy is maintained, but simulation time becomes excessively long (taking many hours or days)
Solution Approach 1:
The circuit simulation is divided into two segments: CPU instructions are simulated using a virtualized processor that executes actual hardware instructions, while only peripheral interactions are simulated using HDL code. This segmentation allows the time-consuming CPU simulation to be handled by the faster virtualized processor rather than the slow HDL simulator.
Solution Approach 2:
A virtualized processor acts as an intermediary between the HDL circuit model and the actual firmware instructions. The virtualized processor receives instructions from the HDL simulation, executes them using real processor hardware, and returns results to the HDL simulator, thereby bridging the gap between simulation accuracy and execution speed.
2Reliability
If complete circuit simulation including CPU instructions is performed using HDL, then comprehensive verification is achieved, but data volume becomes overwhelming and error analysis becomes difficult
Solution Approach 1:
CPU instruction execution is extracted from the HDL simulation environment and placed in the virtualized processor. Only the peripheral interactions and system-level behavior remain in the HDL simulation, significantly reducing the volume of simulation data while maintaining verification of the critical peripheral interfaces.
3Productivity
If all firmware instructions are executed on the virtualized processor, then execution speed increases, but simulation accuracy for peripheral interactions may be compromised
Solution Approach 1:
Different execution methods are applied to different parts of the firmware: CPU instructions are executed on the virtualized processor for speed, while peripheral interactions are simulated using HDL code for accuracy. This local differentiation allows each component to be handled by the most appropriate method for its specific requirements.
Data Source
AI summary
Embodiments of the present disclosure include techniques for simulating circuits, such as systems-on-a-chip (SoC). In various embodiments, a circuit being simulated may comprise one or more processors. However, simulation of the circuit using a hardware description language (HDL) may use a virtualized processor to execute firmware instructions rather than simulating the processor using HDL. Certain instructions from the virtualized processor may be sent, during simulation, to the HDL simulation for execution.