Virtualized Scan Chain Testing in RAM Arrays
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Solution Overview
Problem
Conventional memory systems require external Built-In Self-Test (BIST) circuits to test memory arrays, which consume additional die area and increase testing latency, especially for static random access memory (SRAM) cells that are not scannable in serialized fashion.
Innovation Solution
Incorporating an integrated test circuit within the memory array to create a virtualized scan chain, allowing serialized test data to be written and read internally, eliminating the need for an external BIST circuit and reducing testing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external BIST circuits are used to test memory arrays, then memory functionality can be tested, but die area is consumed and testing latency increases
Solution Approach 1:
The patent merges the test circuit functionality directly into the memory array structure by utilizing existing memory cells and circuitry. The memory cells are reconfigured to serve dual purposes: normal memory operation and test operations. This integration eliminates the need for separate external BIST circuits, thereby reducing die area while maintaining testing capability.
Solution Approach 2:
The patent implements multi-functionality by enabling memory cells to operate in both normal memory mode and test mode. The same physical infrastructure (memory cells, bit lines, word lines) is used for both data storage and test pattern generation/verification. This universal usage reduces the need for dedicated test hardware, conserving die area.
2Reliability
If external BIST circuits are used to test memory arrays, then memory functionality can be tested, but testing latency increases
Solution Approach 1:
The patent prepares the memory array for testing by pre-configuring the internal circuitry and test patterns before actual testing begins. The integrated test circuit is ready within the memory structure, eliminating the need for external circuit setup time. Test patterns are generated and applied internally, reducing the overall testing latency.
3Area of stationary object
If 6T-based SRAM cells are used instead of flip-flop circuits, then area and power are conserved, but scannability is lost
Solution Approach 1:
The patent introduces dynamic reconfiguration capability to 6T-SRAM cells, allowing them to switch between normal memory operation and test mode. During test mode, the cells are dynamically controlled to enable serialized access patterns, achieving scannability without changing the fundamental 6T structure. This dynamic behavior preserves area efficiency while adding test functionality.
Solution Approach 2:
The patent changes the operational parameters of 6T-SRAM cells during test mode, including control signal timing, word line activation sequences, and bit line sensing patterns. These parameter modifications enable the cells to function in a serialized scan chain manner, achieving scannability while maintaining the area-efficient 6T structure.
Data Source
AI summary
Virtualized scan chain testing in a random access memory array, and related methods and computer-readable media are disclosed. To facilitate virtualized scan chain testing, the memory array includes an integrated test circuit that causes the memory array to behave as a serialized scan chain. The integrated test circuit forces serialized write and read access to offset entries in the memory array on each scan cycle in a scan mode based on received serialized test data. After the number of scan cycles equals the number of entries the memory array, the entries in the memory array are fully initialized with test data from the serial test data flow. In subsequent scan cycles, the integrated test circuit continues to perform serial read operations to cause stored serial test data to be serially shifted out as an output serial data flow that then be compared to the original serial test data.