Virtually Indexed Physically Tagged Cache Aliasing Resolution
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Solution Overview
Problem
Aliasing in virtually indexed, physically tagged caches can lead to duplication and coherency issues, reducing the effective cache size and causing complications due to multiple virtual addresses mapping to the same physical address.
Innovation Solution
Incorporating snoop request processing circuitry to determine possible virtual address portions for a given physical address, performing snoop processing operations to detect hit conditions, and executing coherency actions to address aliasing by invalidating cache entries and managing cache coherency, while using a Check Alias Table to handle non-allocating store requests and buffer circuitry to manage physical addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a virtually indexed, physically tagged cache is used to enable parallel cache lookup and address translation, then cache access speed is improved, but aliasing occurs when different virtual addresses map to the same physical address, causing cache duplication and coherency issues
Solution Approach 1:
The cache indexing mechanism is segmented into two independent parts: virtual address indexing for fast parallel lookup and physical address tagging for accurate hit/miss determination. This segmentation allows the cache to benefit from virtual address diversity while using physical address verification to eliminate aliasing errors, thus resolving the contradiction between speed and reliability
Solution Approach 2:
The physical address tag acts as an intermediary verification layer between the virtual address index and the cache data. When a cache line is accessed via virtual address indexing, the physical address tag is compared to confirm the actual physical address match, preventing false hits from aliased virtual addresses and ensuring cache coherency while maintaining fast access
2Adaptability or versatility
If aliasing is allowed with multiple virtual addresses mapping to the same physical address, then address space flexibility is improved, but cache duplication occurs reducing effective cache size
Solution Approach 1:
The cache address verification process is segmented into virtual address indexing (for flexibility) and physical address tagging (for deduplication). This allows the system to accept multiple virtual addresses mapping to the same physical address while using the physical tag comparison to identify and prevent duplicate cache entries, thereby maintaining address space flexibility while preserving effective cache size
Solution Approach 2:
The cache verification parameter is changed from virtual address matching to physical address tag matching. By using physical address tags for the final hit/miss determination, the cache can accommodate virtual address aliasing without creating duplicate entries, thus maintaining address space flexibility while preventing cache size reduction from duplication
Data Source
AI summary
An apparatus and method are provided for operating a virtually indexed, physically tagged cache. The apparatus has processing circuitry for performing data processing operations on data, and a virtually indexed, physically tagged cache for storing data for access by the processing circuitry. The cache is accessed using a virtual address portion of a virtual address in order to identify a number of cache entries, and then physical address portions stored in those cache entries are compared with the physical address derived from the virtual address in order to detect whether a hit condition exists. Further, snoop request processing circuitry is provided that is responsive to a snoop request specifying a physical address, to determine a plurality of possible virtual address portions for the physical address, and to perform a snoop processing operation in order to determine whether the hit condition is detected for a cache entry when accessing the cache storage using the plurality of possible virtual address portions. On detection of the hit condition a coherency action is performed in respect of the cache entry causing the hit condition. This allows effective detection and removal of aliasing conditions that can arise when different virtual addresses associated with the same physical address cause cache entries in different sets of the cache to be accessed.