VISC Framework Compiler-Architecture Interaction for Microprocessor Security
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Solution Overview
Problem
Current microprocessors are vulnerable to reengineering of program executables and physical microprobing, leading to compromised security, especially in tamper-resistant systems, due to their fixed Instruction Set Architecture (ISA) and ease of disassembly of instruction opcodes, which also affects energy and performance considerations.
Innovation Solution
The introduction of a Virtual Instruction Set Computing (VISC) framework that reconfigures instruction opcodes at a fine compiler-managed granularity, providing a secure execution environment through a tightly integrated compiler-architecture interaction, using static control instructions and cryptography to scramble and unscramble instructions, ensuring unique binary execution without significant impact on chip area, performance, or power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a fixed Instruction Set Architecture (ISA) is used in microprocessors, then device complexity is reduced and ease of manufacture is improved, but security is compromised due to ease of disassembly and reengineering of program executables
Solution Approach 1:
The patent implements a reconfigurable ISA that dynamically changes instruction encoding and decoding behavior at runtime. The processor can switch between different ISA configurations, making static analysis and reverse engineering ineffective. This dynamic reconfiguration capability maintains ease of manufacture through standardized processor structures while dramatically improving security against reengineering attacks.
Solution Approach 2:
The patent changes the parameters of the ISA by introducing variable instruction encoding schemes where opcode meanings and operand interpretations can be modified through configuration registers. This allows the same physical processor to present different instructional semantics to software, preventing attackers from reliably interpreting binary code without knowledge of the current configuration state.
2Reliability
If the ISA is made reconfigurable to improve security, then security is improved, but device complexity increases and manufacturing becomes more difficult
Solution Approach 1:
The patent designs a universal processor core that can function in multiple ISA modes through a single reconfigurable decoding unit. Rather than requiring separate hardware for each ISA configuration, the same processor infrastructure supports multiple instructional semantics by changing configuration parameters, thereby reducing overall device complexity while maintaining security.
Solution Approach 2:
The patent introduces an intermediary configuration layer between the fixed hardware and the variable instructional semantics. Configuration registers and control logic act as mediators that translate between stable physical structures and dynamic instructional behavior, allowing security improvements without proportionally increasing hardware complexity.
3Reliability
If reconfigurable ISA technology is added to existing processor cores, then security is improved, but chip area increases
Solution Approach 1:
The patent segments the reconfiguration capability into modular configuration registers and control logic that can be integrated alongside existing processor cores. Rather than redesigning the entire processor, the security features are divided into discrete functional blocks that can be added to commercial off-the-shelf (COTS) cores with minimal area overhead.
4Reliability
If instruction opcodes are scrambled to prevent disassembly, then security is improved, but instruction decoding complexity increases
Solution Approach 1:
The patent performs preliminary configuration setup during processor initialization or before executing protected code sections. Configuration registers are pre-loaded with decoding parameters that define the current opcode mapping, allowing the main decoding logic to operate with simple table lookups rather than complex real-time calculations, thereby reducing operational decoding complexity.
Data Source
AI summary
A method, for use in a processor context, wherein instructions in a program executable are encoded with plural instruction set encodings. A method wherein a control instruction encoded with an instruction set encoding contains information about decoding of an instruction that is encoded with another instruction set encoding scheme. A method wherein instruction set encodings are randomly generated at compile time. A processor framework wherein an instruction is decoded during execution with the help of information provided by a previously decoded control instruction.