Programmable Vision Accelerator Self-Test for VPU Fault Isolation
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Solution Overview
Problem
Conventional vector processing units (VPUs) face inefficiencies in detecting min/max values, operand sharing among data lanes, memory access, table lookups, and fault detection, leading to increased latency and processing complexity in applications like computer vision and deep learning.
Innovation Solution
The proposed solution includes a min/max hardware collector, automatic predication, enhanced SIMD architecture with lane communication, transposed load/store operations, load with permute instructions, and a decoupled lookup table accelerator, along with a hardware sequencer for DMA systems to improve data movement and processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional solutions write all values to memory and perform analysis in memory, then complete value analysis is achieved, but additional processing cycles are required
Solution Approach 1:
The patent extracts the min/max detection function from general-purpose memory operations by implementing dedicated hardware circuits (min/max detectors) that operate independently within the VPU data path, allowing simultaneous value computation and extremum detection without requiring complete memory writes
Solution Approach 2:
The patent performs preliminary min/max detection during the data processing pipeline by inserting detection circuits that continuously monitor intermediate values as they flow through computation stages, enabling early identification of extremum values before final memory storage is required
2Productivity
If high clock rate processors perform software pipelining and loop unrolling to achieve high throughput, then processing speed increases, but code size and latency increase due to remainder loops
Solution Approach 1:
The patent implements self-service mechanisms where the VPU automatically handles iteration counting and remainder loop management through dedicated control logic that monitors execution progress and dynamically adjusts unrolling factors, eliminating the need for manual compiler intervention and reducing code complexity
3Productivity
If SIMD units operate independently in parallel data lanes with limited sharing, then processing parallelism is achieved, but operand copying increases processing complexity
Solution Approach 1:
The patent merges previously separate operand storage locations by implementing a shared operand buffer that all SIMD data lanes can access simultaneously, allowing multiple lanes to operate in parallel without requiring independent copies of common operands, thereby reducing memory bandwidth requirements and simplifying data management
4Stability of the object's composition
If memory reads use standard units equal to vector processing width, then memory access consistency is maintained, but unnecessary values are read when memory bank is wide
Solution Approach 1:
The patent segments the wide memory bank into multiple narrower sub-banks, each capable of independent access with finer granularity control. This allows the system to read only the specific number of values needed (e.g., 60 values) by accessing appropriate subsets of sub-banks, rather than reading complete wide memory words that include unnecessary data
5Speed
If tables are replicated for each value or additional read ports are added to memory banks, then table lookup speed increases, but additional memory and chip space are required
Solution Approach 1:
The patent implements continuous table lookup capability by adding multiple read ports to existing memory banks, allowing multiple values to be retrieved simultaneously from the same table without requiring separate replicated tables. This maintains high lookup speed while avoiding the exponential growth of memory requirements that would result from full replication
6Productivity
If VPU is programmed to execute on smaller set of highly optimized code without data caches, then code efficiency improves, but each memory access requires reading from memory bank even with overlapping data
Solution Approach 1:
The patent implements preliminary data preparation by implementing data caches that pre-load and store frequently accessed data elements. When the VPU executes optimized code sequences with overlapping data access patterns, the cache system proactively retrieves and buffers required data in advance, eliminating repeated memory bank accesses and reducing latency
Data Source
AI summary
In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.