Visualization Constraints for Circuit Design Waveforms
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Solution Overview
Problem
Circuit designers face challenges in generating visualization constraints for complex circuit designs, as existing verification and debugging techniques require fluency in verification languages and are not intuitive, making it difficult to specify desired behaviors effectively.
Innovation Solution
An interactive system that allows circuit designers to generate visualization constraints by overlaying desired signal values onto waveforms, using cursor inputs to indicate desired values, which are then converted into visualization constraints that can be used to generate new waveforms or input into simulation tools, enabling designers to specify desired behaviors without typing temporal expressions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional verification techniques using temporal expressions are used, then verification precision is improved, but ease of operation deteriorates due to requiring fluency in verification languages
Solution Approach 1:
The patent introduces an intermediary system that translates intuitive waveform annotations into formal verification constraints. The waveform display with annotation capabilities serves as a mediator between the designer's intuitive specifications and the formal verification language requirements, allowing designers to specify desired behaviors through visual markers rather than typing temporal expressions directly
Solution Approach 2:
The patent replaces the mechanical system of typing and parsing temporal expressions with a visual interaction system. Instead of requiring designers to manually input verification language code, the system captures cursor positions and waveform annotations, automatically converting them into the appropriate formal constraints, thereby substituting manual text-based operations with automated visual-based operations
2Ease of operation
If waveform annotations are added to indicate desired values, then ease of operation is improved, but device complexity increases due to overlay generation and constraint conversion mechanisms
Solution Approach 1:
The patent merges the waveform display functionality with the constraint specification functionality into a single integrated interface. The waveform display is enhanced with annotation capabilities, allowing desired values to be indicated directly on the waveform visualization. This merging eliminates the need for separate constraint input interfaces and reduces the perceived complexity for the user
Solution Approach 2:
The system performs self-service by automatically generating verification constraints from the annotated waveform data. The constraint generation mechanism autonomously processes the waveform annotations and cursor positions to produce the appropriate formal verification constraints, eliminating the need for manual constraint writing and reducing the operational burden on designers
Data Source
AI summary
A first waveform for a circuit design is received. The first waveform includes at least an actual value of a signal of the circuit design at one or more clock cycles. A user input for a cursor is received, and a signal wave overlay is displayed on the first waveform having an appearance corresponding to a location of the cursor. The signal wave overlay indicates a desired value of the signal at one or more clock cycles that is different than the actual value of the signal in the one or more clock cycles. Based on the desired value of the signal indicated by the signal wave overlay, a visualization constraint for the circuit design is generated. The visualization constraint is used to generate a second waveform, where the visualization constraint restricts the second waveform.