Viterbi Decoder Using Correlation Metrics Instead of LLR

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Solution Overview

Problem

Existing Viterbi decoding methods require complex calculations of log-likelihood ratios (LLR) which can be error-prone and limit decoding performance, especially with direct sequence spread spectrum (DSSS) and offset-quadrature phase shift keying (O-QPSK) modulation.

Innovation Solution

A decoder that determines a survivor path based on correlation values without calculating LLR, using correlation values as branch metrics to trace back the path and restore the original signal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If log-likelihood ratio (LLR) calculation is performed for Viterbi decoding, then decoding accuracy can be maintained, but computational complexity and hardware requirements increase significantly

Engineering Contradiction:
Improvedecoding accuracyVSAvoidhardware complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the LLR calculation step from the Viterbi decoding process. By using correlation values directly as branch metrics without converting them to LLR, the invention removes the complex logarithmic and exponential operations while maintaining decoding accuracy through direct correlation-based metric computation.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the parameter representation from LLR (log-likelihood ratio) to direct correlation values. This parameter transformation allows the decoder to work with raw correlation metrics from the despreader, avoiding the computational overhead of LLR calculation while preserving the essential information needed for accurate path selection.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If LLR calculation is performed for each symbol in the demodulation signal, then decoding performance can be optimized, but processing time and computational load increase

Engineering Contradiction:
Improvedecoding performanceVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary correlation calculation during the despreading stage, storing the correlation values for direct use in Viterbi decoding. By pre-computing and retaining these correlation metrics, the invention eliminates the need for time-consuming LLR calculation during the decoding phase, thus reducing processing time while maintaining performance.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent skips the intermediate LLR calculation step entirely, rushing directly from correlation value computation to Viterbi decoding using correlation values as metrics. This shortcut eliminates unnecessary computational steps and reduces processing time while achieving the same decoding performance through direct metric usage.

Inventive Principle:
Principle #21Skipping (Rushing through)

3Measurement precision

If complex LLR calculation algorithms are implemented, then decoding accuracy is maintained, but ease of operation and implementation difficulty worsen

Engineering Contradiction:
Improvedecoding accuracyVSAvoidimplementation ease
Core Design Contradiction:
Measurement precisionVSEase of operation

Solution Approach 1:

The patent enables the decoding system to use the correlation values produced by the despreader directly without requiring additional LLR calculation processing. This self-service approach allows the correlation metrics to serve dual purposes: both for signal detection and for Viterbi decoding, simplifying the overall system operation and implementation.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent makes the correlation value computation serve multiple functions: it is used both for symbol detection and as branch metrics for Viterbi decoding. This multi-functionality eliminates the need for separate LLR calculation circuits, simplifying the system architecture and making implementation easier while maintaining decoding accuracy.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20260031837A1Decoder for viterbi decoding, operation method and electronic device
Publication Date: 2026.01.29 SAMSUNG ELECTRONICS CO LTD
  • US20260031837A1 patent drawing
  • US20260031837A1 patent drawing
  • US20260031837A1 patent drawing

AI summary

A receiver includes a demodulator configured to demodulate a received signal, a despreader configured to, based on a reference chip sequence, perform dispreading on a demodulation signal corresponding to the demodulation of the received signal; and a decoder configured to determine a survivor path for states based on a correlation value corresponding to the despreading, while omitting calculation of a log-likelihood ratio (LLR) for a symbol included in the demodulation signal, and output a decoding signal by tracing back the survivor path.