Viterbi Convolutional Decoder Using Auxiliary Data for Faster Demodulation

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Solution Overview

Problem

In Low-Power Wide-Area Network (LPWAN) systems, devices face high power consumption due to extended computing times required for accurate signal demodulation in poor signal-to-noise ratio environments, which increases battery drain and costs.

Innovation Solution

A convolutional code decoder and decoding method that utilizes auxiliary data for error detection and channel coding, coupled with a Viterbi decoding circuit to quickly demodulate signals, reducing the demodulation time and power consumption by leveraging predicted data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the receiving end waits for repeatedly transmitted signals to improve demodulation accuracy, then the bit error rate performance is improved, but the power consumption increases

Engineering Contradiction:
Improvebit error rate performanceVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies preliminary action by performing error detection on auxiliary data before full decoding. The error detection data generation circuit processes the auxiliary data to generate error detection results, which are then used to determine whether full Viterbi decoding is necessary. This preliminary error detection step allows the system to avoid power-consuming full decoding operations when errors are detected, thereby reducing overall power consumption while maintaining reliable communication.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If the receiving end waits for repeatedly transmitted signals, then the demodulation accuracy is improved, but the computing time is extended

Engineering Contradiction:
Improvedemodulation accuracyVSAvoidcomputing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent performs error detection on auxiliary data as a preliminary step before full decoding. The error detection data generation circuit quickly processes the auxiliary data to generate error detection results, enabling the system to determine early whether full Viterbi decoding is required. This preliminary action reduces the overall computing time by avoiding unnecessary full decoding operations while maintaining accurate demodulation through selective decoding based on error detection outcomes.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If conventional decoding methods are used, then the system operates reliably in poor SNR environments, but the operation duration is extended

Engineering Contradiction:
Improveoperation reliability in poor SNRVSAvoidoperation duration
Core Design Contradiction:
ReliabilityVSDuration of action of moving object

Solution Approach 1:

The patent implements a preliminary error detection step that processes auxiliary data before full decoding. The error detection data generation circuit quickly analyzes the auxiliary data to generate error detection results, which determine whether full Viterbi decoding is necessary. This two-stage approach maintains reliable operation in poor SNR environments by performing robust decoding when needed, while reducing operation duration by skipping full decoding when error detection indicates good signal quality.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10826541B2Convolutional code decoder and convolutional code decoding method
Publication Date: 2020.11.03 REALTEK SEMICON CORP
  • US10826541B2 patent drawing
  • US10826541B2 patent drawing
  • US10826541B2 patent drawing

AI summary

The invention discloses a convolutional code decoder and a convolutional code decoding method. The convolutional code decoder performs decoding operation according to a received data and an auxiliary data to obtain a target data and includes an error detection data generation circuit, a channel coding circuit, a selection circuit, and a Viterbi decoding circuit. The error detection data generation circuit performs an error detection operation on the auxiliary data to obtain an error detection data. The channel coding circuit, coupled to the error detection data generation circuit, performs channel coding on the auxiliary data and the error detection data to obtain an intermediate data. The selection circuit, coupled to the channel coding circuit, generates a to-be-decoded data according to the received data and the intermediate data. The Viterbi decoding circuit, coupled to the selection circuit, decodes the to-be-decoded data to obtain the target data.