Viterbi Equalizer Segmentation for Severe Multipath Channels

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Solution Overview

Problem

Conventional Viterbi equalizers face significant computational complexity due to exponential growth in calculation with increasing length of the tapped delay line module, leading to inefficiencies in handling severe multipath channel conditions.

Innovation Solution

A Viterbi equalizer architecture that filters out secondary interferences and splits the received signal into multiple sequences, each with a reduced tapped delay line length, allowing for a simplified Viterbi equalizing process using a serial to parallel converter and a Viterbi equalizing module, which significantly reduces computational requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the length of the tapped delay line module is increased to handle severe multipath channel conditions, then the ability to eliminate inter-symbol interference is improved, but the computational complexity increases exponentially

Engineering Contradiction:
Improveinter-symbol interference elimination capabilityVSAvoidcomputational complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the received signal into multiple parallel sequences using a serial-to-parallel converter, where each sequence is processed by a separate Viterbi equalizer with a shorter tapped delay line. This segmentation approach maintains the overall interference elimination capability while reducing the computational burden on each individual processing unit, thereby resolving the contradiction between reliability and device complexity.

Inventive Principle:
Principle #1Segmentation

2Reliability

If a conventional Viterbi equalizer is used to handle severe multipath conditions, then inter-symbol interference is effectively eliminated, but the calculation amount increases significantly

Engineering Contradiction:
Improveinter-symbol interference elimination capabilityVSAvoidcalculation efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the single complex Viterbi equalizing task into multiple simpler parallel tasks. By using a serial-to-parallel converter to create multiple sequences and processing them simultaneously with shorter delay lines, the system achieves the same interference elimination performance with significantly improved calculation efficiency and reduced computational requirements.

Inventive Principle:
Principle #1Segmentation

3Adaptability or versatility

If the tapped delay line module length is increased, then the coverage of multipath interference is improved, but the amount of calculation increases exponentially

Engineering Contradiction:
Improvemultipath channel coverageVSAvoidcalculation complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent achieves comprehensive multipath coverage by distributing the processing across multiple parallel Viterbi equalizers, each handling a portion of the interference. The serial-to-parallel converter enables this segmentation, allowing the system to maintain high adaptability to severe multipath conditions while keeping each individual equalizer's complexity manageable through shorter delay lines.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8937995B2Equalizer and equalizing method thereof
Publication Date: 2015.01.20 REALTEK SEMICON CORP
  • US8937995B2 patent drawing
  • US8937995B2 patent drawing
  • US8937995B2 patent drawing

AI summary

An equalizer and an equalizing method for equalizing a received signal, where the received signal includes at least one primary interference and a plurality of secondary interferences. The Viterbi equalizer includes a filter module for filtering out the secondary interferences from the received signal to generate a filtered signal, a serial to parallel converter, coupled to the filter module, for generating a plurality of sequences according to the filtered signal, and a Viterbi equalizing module, coupled to the serial to parallel converter, for respectively equalizing the plurality of sequences to generate a plurality of equalized sequences. The architecture of the Viterbi equalizing module is greatly simplified thereby reducing the calculation activity of the Viterbi equalizer as well as maintaining its efficiency.