Viterbi Survivor Memory Architecture for Low-Latency Parallel Decoding
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Solution Overview
Problem
Current methods for decoding convolutionally encoded telecommunications signals face challenges in efficiency, power consumption, and latency, particularly in mobile devices, due to high decoding complexity and simultaneous read/write access requirements in register exchange approaches, and increased latency in trace-back methods.
Innovation Solution
The proposed solution involves parallel processing of trellis searches, trace-forward, and trace-back operations using multiple dedicated memory registers and multiplexers, allowing for simultaneous storage and output of decision bits in various registers and RAM, with tail-biting checks to optimize decoding efficiency and reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If register exchange approach is used to store Viterbi survivor paths, then decoding speed is improved, but power consumption increases and battery life decreases
Solution Approach 1:
The patent segments the decoding process into distinct phases (trellis search, trace-back, trace-forward) and uses separate memory structures for each phase. The trace-back unit uses a stack-based memory structure while the trace-forward unit uses a queue-based memory structure, allowing parallel processing with reduced simultaneous memory access requirements, thereby reducing power consumption while maintaining decoding speed.
Solution Approach 2:
The patent implements dynamic memory allocation and access patterns where the memory structures are updated and accessed in a staggered manner rather than simultaneously. The trace-back and trace-forward operations can proceed in parallel with dynamic coordination of memory access, reducing the peak power consumption associated with simultaneous read/write operations.
2Quantity of substance
If trace-back approach is used to decode Viterbi-encoded data, then memory requirements are reduced, but latency increases due to inverse-ordered output
Solution Approach 1:
The patent performs preliminary trace-forward operations during the trellis search phase to pre-calculate and store the forward trace information in a queue-based memory structure. This preliminary action allows the final decoding output to be generated in correct order without requiring additional latency for inversion, as the forward trace information is already prepared in advance.
Solution Approach 2:
The patent merges the trace-back and trace-forward operations into a unified decoding architecture where both operations proceed in parallel and their results are combined to produce the final decoded output in correct order. This merging eliminates the need for separate inverse-order processing and LIFO unit inversion, reducing overall latency.
3Reliability
If simultaneous read and write access to all L×N registers is required, then decoding accuracy is maintained, but power consumption increases
Solution Approach 1:
The patent segments the memory access operations into distinct time phases and spatial locations. The trellis search phase writes to survivor path memory while the trace-back phase reads from stack-based memory, and the trace-forward phase reads from queue-based memory. This segmentation allows different memory structures to be accessed at different times and locations, maintaining decoding accuracy while reducing simultaneous access power consumption.
Solution Approach 2:
The patent introduces intermediary memory structures (stack-based and queue-based memory) that buffer and coordinate data flow between the trellis search unit and the output units. These intermediaries allow asynchronous processing and reduce the need for simultaneous read/write access to the same memory locations, thereby reducing power consumption while maintaining data integrity and decoding accuracy.
Data Source
AI summary
In various aspects, the disclosure describes systems and methods for decoding of convolutionally encoded signals representing, for example, telecommunications signals such as command or content signals used in digital telecommunications. In various embodiments such aspects of the disclosure provide systems and methods for improving the efficiency, speed, and power consumption of such processes by providing architectures and methods for processing various parts of the encoded data records in parallel, using multiple and optionally specially-designed, dedicated memory registers and multiplexers.